System and method for using multiple global identification subnet prefix values in a network switch environment in a high performance computing environment. A packet is received from a network fabric by a first Host Channel Adapter (HCA). The packet has a header portion including a destination subnet prefix identifying a destination subnet of the network fabric. The network HCA is allowed to receive the first packet from a port of the network HCA by selectively determining a logical state of a flag and, selectively in accordance with a predetermined logical state of the flag, ignoring the destination subnet prefix identifying the destination subnet of the network fabric.

System and method for using multiple global identification subnet prefix values in a network switch environment in a high performance computing environment. A packet is received from a network fabric by a first Host Channel Adapter (HCA). The packet has a header portion including a destination subnet prefix identifying a destination subnet of the network fabric. The network HCA is allowed to receive the first packet from a port of the network HCA by selectively determining a logical state of a flag and, selectively in accordance with a predetermined logical state of the flag, ignoring the destination subnet prefix identifying the destination subnet of the network fabric.

A multi-processor system with a portion of content-addressable memory (CAM) configured as a tuple space to control data flow between processing element. A writing processor may write to a tuple space followed by a reading processor reading from the tuple space. However the system may control access to the tuple space so that no read operations may be performed for a particular tuple space before that space is written to. Further, no write operations may be performed to the tuple space prior to previous written data being read from the tuple space. A processor wishing to use the tuple space before being permitted to do so may be stalled, thus controlling data flow between operating processors.

A parallel turbine ternary content addressable memory includes one or more atoms in each of one or more rows, wherein each of the one or more atoms includes a memory with N addresses and a width of M logical lookup entries, wherein N and M are integers, one or more result registers, each with a width of M, wherein a number of the one or more result registers equals a number of one or more keys each with a length of N, and a read pointer configured to cycle through a row of the N addresses per clock cycle for comparison between the M logical entries and the one or more keys with a result of the comparison stored in an associated result register for each of the one or more keys.

Access is obtained to a truth table having a plurality of rows, each including a plurality of input bits and a plurality of output bits. At least some rows include don't-care inputs. At least some of the rows are clustered into a plurality of multi-row clusters. At least some of the multi-row clusters are assigned to ternary content-addressable memory modules of a prefabricated programmable memory array. Instructions for interconnecting the ternary content-addressable memory modules with a plurality of input pins of the prefabricated programmable memory array and a plurality of output pins of the prefabricated programmable memory array are specified in a data structure, in order to implement the truth table.

Access is obtained to a truth table having a plurality of rows, each including a plurality of input bits and a plurality of output bits. At least some rows include don't-care inputs. At least some of the rows are clustered into a plurality of multi-row clusters. At least some of the multi-row clusters are assigned to ternary content-addressable memory modules of a prefabricated programmable memory array. Instructions for interconnecting the ternary content-addressable memory modules with a plurality of input pins of the prefabricated programmable memory array and a plurality of output pins of the prefabricated programmable memory array are specified in a data structure, in order to implement the truth table.

In one embodiment, an associative memory is built using multiple cascaded associative memory blocks, with stored lookup words spanning a same or different numbers of associative memory blocks. A first lookup operation is performed by a first associative memory to generate first matching indications of associative entries of the first associative memory that match both the first lookup word and the first lookup type. A second lookup operation is performed by an end associative memory to generate end matching indications of associative entries of the end associative memory that match both the end lookup word and the end of word lookup type. A final lookup result indicating a matching multi-block spanning associative memory entry based on the first matching indications and the end matching indications is determined and signaled by the associative memory is built using multiple cascaded associative memory blocks.

In one embodiment, an associative memory is built using multiple cascaded associative memory blocks, with stored lookup words spanning a same or different numbers of associative memory blocks. A first lookup operation is performed by a first associative memory to generate first matching indications of associative entries of the first associative memory that match both the first lookup word and the first lookup type. A second lookup operation is performed by an end associative memory to generate end matching indications of associative entries of the end associative memory that match both the end lookup word and the end of word lookup type. A final lookup result indicating a matching multi-block spanning associative memory entry based on the first matching indications and the end matching indications is determined and signaled by the associative memory is built using multiple cascaded associative memory blocks.

Provided herein are a power-on reset circuit and a semiconductor memory device including the same. The power-on reset circuit may include: a voltage dividing circuit suitable for dividing an external power supply voltage to output a reference voltage, an output node control circuit suitable for controlling a potential level of an output node to an external power supply voltage level or a ground power supply voltage level in response to the reference voltage, and a buffer circuit suitable for buffering the potential level of the output node to output a power-on reset signal. In the voltage dividing circuit, a potential level of the reference voltage in a power up period is different from a potential level of the reference voltage in a power down period.

Technology for an apparatus is described. The apparatus can include a memory and a storage controller. The storage controller can be configured to receive a search command with one or more parameters that instructs the storage controller to search for a data pattern in data stored in the memory. The storage controller can be configured to search the data stored in the memory for the data pattern according to the one or more parameters included in the search command. The storage controller can be configured to locally search the data in the memory for the data pattern without transferring the data to a processor to perform the search.