According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.

Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The memory cell string can include a body associated with the memory cells. At least one of such embodiments can include a module configured to apply a negative voltage to at least a portion of the body of the memory cell string during an operation of the apparatus. The operation can include a read operation, a write operation, or an erase operation. Other embodiments are described.

A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.

Aspects of a storage device including a memory and a controller are provided which allow for reduction of current in open blocks during read operations using read voltage ramp rate control. The controller determines whether a block is open or closed. If the block is closed, the controller causes a read voltage to be applied to one of the block's word lines at a first ramp rate. If the block is open, the controller causes a read voltage to be applied to another of the block's word lines at a slower, second ramp rate. The controller further causes a read voltage to be applied to another word line of the open block at a different, third ramp rate. Thus, read voltages for open blocks may ramp slower than read voltages for closed blocks, as well as ramp at different rates for different word lines in open blocks.

A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first plurality of NMOS transistors in series with a first input node and a negative amplified voltage, and the second leg includes a second plurality of NMOS transistors in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.

A programming method for a three-dimensional ferroelectric memory device is disclosed. The programming method includes applying a first voltage on a selected word line of a target memory cell. The target memory cell has a first logic state and a second logic state corresponding to a first threshold voltage and a second threshold voltage, respectively. The first and second threshold voltages are determined by two opposite electric polarization directions of a ferroelectric film in the target memory cell. The programming method also includes applying a second voltage on a selected bit line, where a voltage difference between the first and second voltages has a magnitude larger than a coercive voltage of the ferroelectric film such that the target memory cell is switched from the first logic state to the second logic state.

A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.