The present application provides a programmable memory device. The programmable memory device includes an active region, a gate structure and an anti-fuse storage unit. The active region is formed in a substrate and having a linear top view shape. The gate structure is disposed on the substrate and having a linear portion intersected with a section of the active region away from end portions of the active region. The anti-fuse storage unit uses a portion of the active region as a terminal, and further comprises an electrode and a dielectric layer. The electrode is disposed on the portion of the active region and spaced apart from the gate structure, and the dielectric layer is sandwiched between the portion of the active region and the electrode.

Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. The method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.

A liquid discharge head having an element board including an element configured to discharge a liquid includes a first storage element and a second storage element. The first storage element is a fuse element or an anti-fuse element. The second storage element is a semiconductor memory capable of holding a larger capacity than the first storage element. The second storage element is provided on an area other than the element board.

A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.

A method for writing into a one-time programmable memory of an integrated circuit includes attempting, by a memory control circuit of the integrated circuit, to write data in at least one first register of the one-time programmable memory; verifying, by the memory control circuit, whether the data has been correctly written in the at least one first register; and, in case the data has not been correctly written in the at least one first register, attempting, by the memory control circuit, to write the data in at least one second register of the one-time programmable memory.

A method for writing into a one-time programmable memory of an integrated circuit includes attempting, by a memory control circuit of the integrated circuit, to write data in at least one first register of the one-time programmable memory; verifying, by the memory control circuit, whether the data has been correctly written in the at least one first register; and, in case the data has not been correctly written in the at least one first register, attempting, by the memory control circuit, to write the data in at least one second register of the one-time programmable memory.

The disclosed method may include detecting, by a control circuit coupled to a first read only memory (ROM) device and a second ROM device, a failure of a first output signal from the first ROM device to a common output. The first ROM device is connected to the common output and the second ROM device is disconnected from the common output. The method also includes switching, by the control circuit in response to detecting the failure, the common output from the first ROM device to the second ROM device. Various other methods, systems, and computer-readable media are also disclosed.

The disclosed method may include detecting, by a control circuit coupled to a first read only memory (ROM) device and a second ROM device, a failure of a first output signal from the first ROM device to a common output. The first ROM device is connected to the common output and the second ROM device is disconnected from the common output. The method also includes switching, by the control circuit in response to detecting the failure, the common output from the first ROM device to the second ROM device. Various other methods, systems, and computer-readable media are also disclosed.

A memory circuit includes a non-volatile memory cell, a sense amplifier coupled to the non-volatile memory cell, and configured to generate a first output signal, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier.

An electronic device includes a row control circuit and a programming circuit. The row control circuit is suitable for activating a synthesis word line selection signal for enabling a first fuse cell and a second fuse cell in a first mode. In addition, the row control circuit is suitable for activating one of a first fuse access signal for storing fuse data in the first fuse cell or outputting the fuse data from the first fuse cell and a second fuse access signal for storing the fuse data in the second fuse cell or outputting the fuse data from the second fuse cell. The programming circuit is configured to store the fuse data in one of the first and second fuse cells based on the synthesis word line selection signal and the first and second fuse access signals in the first mode.