An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.

An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.

A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

A semiconductor storage device according to the present embodiment includes an antifuse element and a first element. The antifuse element is connected at one end to a first terminal to which a write voltage is applicable, and includes a gate oxide film. The first element is connected to the other end of the antifuse element. In a case where the write voltage that breaks the gate oxide film is supplied to the first terminal and the gate oxide film is not broken, the first element supplies a second potential that makes a potential difference between the one end and the other end less than a potential that breaks the gate oxide film, to the other end.

A memory circuit includes a first bank of non-volatile memory (NVM) devices, a first plurality of decoders, a first plurality of high-voltage (HV) drivers corresponding to the first plurality of decoders, and a first plurality of HV power switches. A first HV power switch is coupled to each HV driver of the first plurality of HV drivers, and each decoder is configured to generate an enable signal corresponding to a column of the first bank of NVM devices. Each HV driver is configured to output a HV activation signal to the corresponding column of the first bank of NVM devices responsive to a power signal of the first HV power switch and to the enable signal of the corresponding decoder.

Systems and methods are provided that sense a state of a fuse located in a fuse array. These methods involve a logic gate that selectively transmits outputs from respective comparators based on the combination of outputs received at the logic gate. The comparators generate outputs based on comparing a signal received indicative of the fuse state and a reference voltage. The described systems and methods reduce power consumption of a fuse sensing device since portions of the fuse sensing device are deactivated when not sensing and enable single fuse reading to occur, among other advantages.

A method and apparatus are described for OTP control logic with randomization for sensing and writing fuse values. In an embodiment, OTP control logic has an address counter to determine an address of a fuse to be read from an OTP fuse box and a corresponding address of a shadow register, a fuse box addressing circuit to read a fuse value from a fuse of the fuse box, a clock circuit coupled to the address counter to provide a clock signal to the address counter, and a randomization circuit to interrupt the clock signal at random times to prevent the address counter from determining a next address in response to the clock signal.

A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Methods, apparatus, systems and articles of manufacture are disclosed to improve performance while reading a one-time programmable memory. An example apparatus includes: a voltage boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and a multiplexer including a first input coupled to the first output of the voltage boost circuit, a second input coupled to the second output of the voltage boost circuit, a third input coupled to an array of memory, and an output coupled to a sensing circuit.

An exemplary semiconductor memory includes a channel region disposed in a semiconductor body, a gate region overlying the channel region, a first and a second source/drain region disposed in the semiconductor body, where the first source/drain region is spaced from the second source/drain region by the channel region. The exemplary memory further includes a first contact electrically contacting the first source/drain region, a second contact electrically contacting the first source/drain region and spaced from the second contact, and a third contact electrically contacting the second source/drain region. The first and second contacts are configured so that a resistivity of the first source/drain region can be irreversibly increased by application of an electric current between the first and second contacts. The first contact extends over a first width, the third contact extends over a third width, where the first width is smaller than the third width.