A magnetic memory device includes a magnetic body having magnetic anisotropy and an insulator including a ferromagnetic element. The magnetic body is structurally connected to both ends of the ferromagnetic insulator, and the magnetic body and the ferromagnetic insulator form a ring shape. An easy axis of the magnetic body is directed in a direction parallel to an opening surface of the ring shape in a whole of the magnetic body.

An electronic device and associated methods including magnonic and electronic circuitry are disclosed. In one example, an array of magnonic elements are interconnected to form a network of spin wave paths, and an electronic pathway is connected to the network of spin wave paths to form a ring circuit.

A system includes a memory device storing a set of start voltage values, wherein the set of start voltage values each represent voltage levels used to initially store charges in performing operations to corresponding one or more memory locations of the memory device; and a processing device, operatively coupled to the memory device, to: determine whether a quantity of start voltage values in the set of start voltage values stored in the memory device meets a threshold; modify the set of start voltage values stored in the memory device to remove one or more start voltage values from the set in response to a determination that the quantity of start voltage values in the set meets the threshold; and add a new start voltage value to the modified set of start voltage values.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

It discloses a technical solution of the present disclosure partitions a high-speed data code stream into a plurality of sequentially arranged data blocks so as to write the data blocks sequentially to a circular cache. The circular cache is comprised of N cache segments that share a write pointer, each cache segment owning an independent read pointer. The data blocks are sequentially written into the N cache segments; data will be continuously written to the 1.sup.st cache segment; data will be read from the cache segment at a relatively low rate and written to a corresponding SD card, thereby implementing data speed reduction; a controller will integrate the disordered data into a same SD card following the original arrangement order, thereby completing all data storage work.

In a method of adaptive buffering in a mobile device having a host processor and a sensor processor coupled with the host processor, the sensor processor is used to buffer data received from a sensor that is operated by the sensor processor. The data is buffered by the sensor processor into a circular data buffer. Responsive to the sensor processor detecting triggering data within the received data: a first adaptive data buffering action is initiated with respect to the data received from the sensor operated by the sensor processor; a second adaptive data buffering action is initiated with respect to second data received from a second sensor of the mobile device; and a command is sent from the sensor processor to a second processor.

In a method of adaptive buffering in a mobile device having a host processor and a sensor processor coupled with the host processor, the sensor processor is used to buffer data received from a sensor that is operated by the sensor processor. The data is buffered by the sensor processor into a circular data buffer. Responsive to the sensor processor detecting triggering data within the received data: a first adaptive data buffering action is initiated with respect to the data received from the sensor operated by the sensor processor; a second adaptive data buffering action is initiated with respect to second data received from a second sensor of the mobile device; and a command is sent from the sensor processor to a second processor.

Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.

A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.