A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

A method for monitoring the operation of a component includes receiving a stream of data samples, wherein each data sample represents a value of a physical parameter of the component, identifying local extrema of the stream of data samples, storing information relating to each local extremum in a respective position of a fixed size buffer, and upon the presence of a cycle formed between two matching endpoints represented by two local maxima or two local minima: i) deleting at least one of the local extrema corresponding to the endpoints of the cycle from the buffer, and ii) storing information related to the cycle in a memory such that the information stored in the memory represents the operation of the component. When the buffer is full such that each position of the buffer contains information relating to a unique local extrema, the method further includes the steps of: i) deleting the information relating to the oldest local extrema from the buffer, ii) calculating a pseudo cycle formed between two endpoints of which one endpoint is represented by the deleted oldest local extrema, and iii) storing information related to the calculated pseudo cycle in the memory.

A method for monitoring the operation of a component includes receiving a stream of data samples, wherein each data sample represents a value of a physical parameter of the component, identifying local extrema of the stream of data samples, storing information relating to each local extremum in a respective position of a fixed size buffer, and upon the presence of a cycle formed between two matching endpoints represented by two local maxima or two local minima: i) deleting at least one of the local extrema corresponding to the endpoints of the cycle from the buffer, and ii) storing information related to the cycle in a memory such that the information stored in the memory represents the operation of the component. When the buffer is full such that each position of the buffer contains information relating to a unique local extrema, the method further includes the steps of: i) deleting the information relating to the oldest local extrema from the buffer, ii) calculating a pseudo cycle formed between two endpoints of which one endpoint is represented by the deleted oldest local extrema, and iii) storing information related to the calculated pseudo cycle in the memory.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.

System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.

A reverse order submission system includes a first memory including a ring buffer, a second memory, and a processor in communication with the first memory. The processor includes a consumer processor and a producer processor, and the producer processor is configured to receive a batch of memory entries. Further, the producer processor is configured to identify a last memory entry in the batch that can be stored in an invalid value slot in the ring buffer, walk the ring buffer backwards, and store each respective memory entry in each respective slot from an end slot to the original slot in the ring buffer. The end slot is a slot associated with the final memory entry ending the batch of memory entries or a slot preceding a valid value slot.

A reverse order submission system includes a first memory including a ring buffer, a second memory, and a processor in communication with the first memory. The processor includes a consumer processor and a producer processor, and the producer processor is configured to receive a batch of memory entries. Further, the producer processor is configured to identify a last memory entry in the batch that can be stored in an invalid value slot in the ring buffer, walk the ring buffer backwards, and store each respective memory entry in each respective slot from an end slot to the original slot in the ring buffer. The end slot is a slot associated with the final memory entry ending the batch of memory entries or a slot preceding a valid value slot.

In a method of adaptive buffering in a mobile device having a host processor and a sensor processor coupled with the host processor, the sensor processor is used to buffer data received from a sensor that is operated by the sensor processor. The data is buffered by the sensor processor into a circular data buffer. Responsive to the sensor processor detecting triggering data within the received data: a first adaptive data buffering action is initiated with respect to the data received from the sensor operated by the sensor processor; a second adaptive data buffering action is initiated with respect to second data received from a second sensor of the mobile device; and a command is sent from the sensor processor to a second processor.