A memory device having: a first local digit line configured to extend in a first direction; a second local digit line configured in parallel with the first local digit line; a plurality of unit cells stacked in the first direction and sandwiched between the first local digit line and the second local digit line, each respective unit cell among the plurality of unit cells configured to connect the first local digit line to the second local digit line in a second direction that is perpendicular to the first direction, the respective unit cell having a transistor and a memory cell; and a plurality of wordlines configured to extend in a third direction that is perpendicular to the first direction and the second direction, where transistors in the plurality of unit cells are connected to the wordlines.

A method begins by determining storage performance for a set of storage resources of the storage network, where data is error encoded into pluralities of sets of encoded data slices in accordance with error encoding parameters, and, for a set of encoded data slices, the error encoding parameters include a decode threshold number and a pillar width threshold number. The method continues by determining a storage provisioning implementation for the set of storage resources based on the storage performance and a storage performance range threshold. The method continues by facilitating the storage provisioning implementation to produce an updated set of storage resources. The method continues by maintaining storage of the set of encoded data slices in accordance with the storage provisioning implementation, where the decode threshold number of encoded data slices of the set of encoded data slices remains available during the facilitating the storage provisioning implementation.