A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, first and second main surfaces opposing each other in a lamination direction, first and second end surfaces opposing each other in a length direction which intersects the lamination direction, and first and second side surfaces opposing each other in a width direction which intersects the lamination direction and the length direction, and external electrodes on the first and second end surfaces, and each electrically connected to the internal electrode layers, wherein the multilayer body includes a slit in at least one of the first side surface, the second side surface, and the second main surface defining and functioning as a board-mounting surface.

A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, first and second main surfaces opposing each other in a lamination direction, first and second end surfaces opposing each other in a length direction which intersects the lamination direction, and first and second side surfaces opposing each other in a width direction which intersects the lamination direction and the length direction, and external electrodes on the first and second end surfaces, and each electrically connected to the internal electrode layers, wherein the multilayer body includes a slit in at least one of the first side surface, the second side surface, and the second main surface defining and functioning as a board-mounting surface.

A micro-isolator is described. The micro-isolator may include a first isolator element, a second isolator element, and a first dielectric material separating the first isolator element from the second isolator element. A second dielectric material may completely or partly encapsulate the second isolator element, or may be present at outer corners of the second isolator element. The second dielectric material may have a larger bandgap than the first dielectric material, and its configuration may reduce electrostatic charge injection into the first dielectric material. The micro-isolator may be formed using microfabrication techniques.

A design method applied to a capacitor array is provided. The capacitor array includes multiple preset capacitor units, and each preset capacitor includes multiple unit capacitors. The method includes: acquiring unit simulation models of the preset capacitor units; acquiring a first simulation model of the capacitor array based on an arrangement manner of the preset capacitor units in the capacitor array and the unit simulation models of the preset capacitor unit; acquiring an arrangement direction of the preset capacitor units based on the arrangement manner, establishing a parasitic resistance equivalent test structure of a group of preset capacitor units in the same arrangement direction; obtaining a parasitic resistance of each preset capacitor unit based on the parasitic resistance equivalent test structure; and establishing a second simulation model representing the capacitor array based on the parasitic resistance of each preset capacitor unit and the first simulation model.

A design method applied to a capacitor array is provided. The capacitor array includes multiple preset capacitor units, and each preset capacitor includes multiple unit capacitors. The method includes: acquiring unit simulation models of the preset capacitor units; acquiring a first simulation model of the capacitor array based on an arrangement manner of the preset capacitor units in the capacitor array and the unit simulation models of the preset capacitor unit; acquiring an arrangement direction of the preset capacitor units based on the arrangement manner, establishing a parasitic resistance equivalent test structure of a group of preset capacitor units in the same arrangement direction; obtaining a parasitic resistance of each preset capacitor unit based on the parasitic resistance equivalent test structure; and establishing a second simulation model representing the capacitor array based on the parasitic resistance of each preset capacitor unit and the first simulation model.

An electronic device includes a fork structure having a pair of arms disposed in spaced relation and defining an open-ended channel therebetween. A surface of channel defines a seat opposite the open end. The channel has a width W.sub.1 at its narrowest section. A rigid wire of an electrical component is disposed in the channel generally adjacent to the seat. The wire has a width W.sub.2 that is greater than the width W.sub.1 so surfaces of the channel at the narrowest section defined by width W.sub.1 interfere with the wire, preventing the wire from moving towards the open end of the channel. The pair of arms are constructed and arranged to be moved toward each other so as to crimp the wire to the fork structure.

An electronic device includes a fork structure having a pair of arms disposed in spaced relation and defining an open-ended channel therebetween. A surface of channel defines a seat opposite the open end. The channel has a width W.sub.1 at its narrowest section. A rigid wire of an electrical component is disposed in the channel generally adjacent to the seat. The wire has a width W.sub.2 that is greater than the width W.sub.1 so surfaces of the channel at the narrowest section defined by width W.sub.1 interfere with the wire, preventing the wire from moving towards the open end of the channel. The pair of arms are constructed and arranged to be moved toward each other so as to crimp the wire to the fork structure.

A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.

A capacitor includes an electrically insulating housing that encloses an interior volume, first and second conductive connection pads that are each configured as externally accessible points of electrical contact to internal electrodes of the capacitor that are disposed within the housing, and an active capacitor dielectric material disposed within the housing and being configured as a dielectric medium between the internal electrodes, the first conductive connection pad having a first planar contact surface that is substantially parallel to a first sidewall of the housing, the second conductive connection pad having a second planar contact surface that is substantially parallel to the first sidewall, the first and second planar contact surfaces being offset from one another in a direction that is orthogonal to the first sidewall.

A capacitor includes an electrically insulating housing that encloses an interior volume, first and second conductive connection pads that are each configured as externally accessible points of electrical contact to internal electrodes of the capacitor that are disposed within the housing, and an active capacitor dielectric material disposed within the housing and being configured as a dielectric medium between the internal electrodes, the first conductive connection pad having a first planar contact surface that is substantially parallel to a first sidewall of the housing, the second conductive connection pad having a second planar contact surface that is substantially parallel to the first sidewall, the first and second planar contact surfaces being offset from one another in a direction that is orthogonal to the first sidewall.