H01G4/00

Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device

A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device

A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

Fan-out semiconductor package

A fan-out semiconductor package may include a support member having a through-hole, a semiconductor chip disposed in the through-hole, a component embedded structure disposed adjacent to and spaced apart from the semiconductor chip in the through-hole by a predetermined distance, an encapsulant, and a connection member. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. The component embedded structure has a plurality of passive components embedded therein. The encapsulant encapsulates at least portions of the support member, the component embedded structure, and the semiconductor chip. The connection member is disposed on the support member, the component embedded structure, and the active surface of the semiconductor chip. The connection member includes redistribution layers and vias electrically connecting the redistribution layers to the plurality of passive components and the connection pads of the semiconductor chip.

Fan-out semiconductor package

A fan-out semiconductor package may include a support member having a through-hole, a semiconductor chip disposed in the through-hole, a component embedded structure disposed adjacent to and spaced apart from the semiconductor chip in the through-hole by a predetermined distance, an encapsulant, and a connection member. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. The component embedded structure has a plurality of passive components embedded therein. The encapsulant encapsulates at least portions of the support member, the component embedded structure, and the semiconductor chip. The connection member is disposed on the support member, the component embedded structure, and the active surface of the semiconductor chip. The connection member includes redistribution layers and vias electrically connecting the redistribution layers to the plurality of passive components and the connection pads of the semiconductor chip.

Method to Determine Properties of a Coating on a Transparent Film, Method for Manufacturing a Capacitor Film and Device to Determine Properties of a Coating on a Transparent Film
20200326177 · 2020-10-15 ·

A method for determining properties of a coating on a transparent film, a method for manufacturing a capacitor film and a device configured to determine properties of a coating on a transparent film are disclosed. In an embodiment a method includes moving the transparent film with the coating on a path which passes between a light source and a sensor, illuminating, by the light source, the coating on the transparent film, detecting, by the sensor, an intensity of transmitted light from the light source and calculating, by a processor, the properties of the coating on the transparent film based on the detected intensity of transmitted light.

Method to Determine Properties of a Coating on a Transparent Film, Method for Manufacturing a Capacitor Film and Device to Determine Properties of a Coating on a Transparent Film
20200326177 · 2020-10-15 ·

A method for determining properties of a coating on a transparent film, a method for manufacturing a capacitor film and a device configured to determine properties of a coating on a transparent film are disclosed. In an embodiment a method includes moving the transparent film with the coating on a path which passes between a light source and a sensor, illuminating, by the light source, the coating on the transparent film, detecting, by the sensor, an intensity of transmitted light from the light source and calculating, by a processor, the properties of the coating on the transparent film based on the detected intensity of transmitted light.

Area-efficient dynamic capacitor circuit for noise reduction in VLSI circuits

A dynamic capacitor circuit having a first passive capacitor, a second passive capacitor, a first terminal of the first passive capacitor and a first terminal of the second passive capacitor connected together to receive an input signal through a resistor. The input signal includes a noise signal component. An alternating current (AC) coupled inverting amplifier has an input connecting a second terminal of the second passive capacitor, the second capacitor coupling the input signal to the AC coupled inverting amplifier input. A conductive path couples an output of the AC coupled inverting amplifier to a second terminal of the first passive capacitor to balance out any noise signal component of the input AC signal at the connection. The dynamic capacitor achieves an amount of noise reduction in a reduced space without applying deep trench capacitors (DTCAP) where the DTCAP is a capacitance formed in a plane perpendicular to the substrate.

Area-efficient dynamic capacitor circuit for noise reduction in VLSI circuits

A dynamic capacitor circuit having a first passive capacitor, a second passive capacitor, a first terminal of the first passive capacitor and a first terminal of the second passive capacitor connected together to receive an input signal through a resistor. The input signal includes a noise signal component. An alternating current (AC) coupled inverting amplifier has an input connecting a second terminal of the second passive capacitor, the second capacitor coupling the input signal to the AC coupled inverting amplifier input. A conductive path couples an output of the AC coupled inverting amplifier to a second terminal of the first passive capacitor to balance out any noise signal component of the input AC signal at the connection. The dynamic capacitor achieves an amount of noise reduction in a reduced space without applying deep trench capacitors (DTCAP) where the DTCAP is a capacitance formed in a plane perpendicular to the substrate.

Method of manufacturing laminated electronic component

A method of manufacturing a laminated electronic component having a circuit element formed in an element body. The method includes forming a collective laminated body including a plurality of element bodies having circuit elements formed therein by laminating pluralities of insulator layers and conductor patterns; forming a plurality of external terminals on one of surfaces of the collective laminated body orthogonal to a lamination direction; forming a disappearing layer covering the external terminals and caused to disappear by heat treatment; cutting and dividing the collective laminated body having the disappearing layer formed thereon along the lamination direction into each of element bodies; applying an insulator precursor to a surface of the element body; and forming a laminated electronic component by applying a heat treatment to the element body to which the insulator precursor is applied. In the method, the insulator layers can be replaced by magnetic material layers.

Capacitor and method of manufacturing the same

A capacitor includes a body, first and second external electrodes, and first and second auxiliary external electrodes. The body includes first and second internal electrodes each having first and second lead portions exposed to one surface of the body. The first and second external electrodes are disposed on the one surface of the body and electrically connected to the first and second internal electrodes, respectively. The first and second auxiliary external electrodes are electrically connected to the first and second external electrodes, respectively, and cover portions of surfaces of the body connected to the one surface of the body.