A method for determining properties of a coating on a transparent film, a method for manufacturing a capacitor film and a device configured to determine properties of a coating on a transparent film are disclosed. In an embodiment a method includes moving the transparent film with the coating on a path which passes between a light source and a sensor, illuminating, by the light source, the coating on the transparent film, detecting, by the sensor, an intensity of transmitted light from the light source and calculating, by a processor, the properties of the coating on the transparent film based on the detected intensity of transmitted light.

A method for determining properties of a coating on a transparent film, a method for manufacturing a capacitor film and a device configured to determine properties of a coating on a transparent film are disclosed. In an embodiment a method includes moving the transparent film with the coating on a path which passes between a light source and a sensor, illuminating, by the light source, the coating on the transparent film, detecting, by the sensor, an intensity of transmitted light from the light source and calculating, by a processor, the properties of the coating on the transparent film based on the detected intensity of transmitted light.

A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

A semiconductor device includes a substrate having a recess region, a first electrode in the recess region and having a three-dimensional network structure, a first dielectric layer in the recess region and covering the first electrode, a second electrode in the recess region and covering the first dielectric layer, and a molding layer filling a remaining portion of the recess region and covering the second electrode.

An electronic component includes conductor layers and insulating resin layers which are alternately stacked on a substrate. One of the insulating resin layers positioned in the lowermost layer is smaller in thickness than the insulating resin layers, and the insulating resin layers are smaller in thermal expansion coefficient than the one of the insulating resin layers. Thus, an element that requires high processing accuracy, such as a capacitor, can be embedded in the insulating resin layer positioned in the lowermost layer and having a small thickness, and an element that requires a sufficient conductor thickness, such as an inductor, can be embedded in the insulating resin layers having a large thickness. In addition, since the insulating resin layers each have a small thermal expansion coefficient, the occurrence of warpage and peeling can be suppressed.

A flexible cable includes an elongated flexible substrate including first and second surfaces on opposite sides thereof, a first capacitor electrode provided on the first surface side of the flexible substrate, the first capacitor electrode extending from a first end of the flexible substrate toward a second end of the flexible substrate, a second capacitor electrode provided on the second surface side of the flexible substrate, the second capacitor electrode extending from the second end of the flexible substrate toward the first end of the flexible substrate, a first connection portion provided at an end of the first capacitor electrode located at the first end of the flexible substrate, and a second connection portion provided at an end of the second capacitor electrode located at the second end of the flexible substrate.

Embodiments herein relate to systems, apparatuses, or processes for forming a decoupling capacitor within a multilayer die using hybrid bonding. Dummy bond pads may be used to form plates for the capacitor and a high-k dielectric material may be deposited between the plates prior to hybrid bonding. Other embodiments may be described and/or claimed.

Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.