The present invention provides a ceramic composition, comprising a primary mixture and a secondary mixture, wherein the primary mixture comprises a first primary ingredient powder and a second primary ingredient powder, and the first primary ingredient powder comprises BaTiO.sub.3, the second primary ingredient powder comprises any of SrTiO.sub.3, Ba.sub.0.95Ca.sub.0.05TiO.sub.3, BaZr.sub.0.1Ti.sub.0.9O.sub.3 or a combination thereof, and the secondary mixture comprises a rare earth oxide, a silicon oxide and an alkaline-earth metal oxide. The present invention further provides a ceramic sintered body obtained by sintering the ceramic composition, and a capacitor comprising the ceramic sintered body and a method for manufacturing the same; wherein the capacitor satisfies EIA-X8R specification, and has a high dielectric constant.

In a planar view of a ceramic capacitor that has low ESL and is embeddable into a substrate, lengths of first and second external electrodes are L1, lengths from portions of the first and second external electrodes farthest from a capacitor main body to portions closer to the capacitor main body by about 40% of a thickness of the first or second external electrode in a laminating direction are L2, a ratio L2/L1 is about 80% or more and about 90% or less. In the planar view, a length of a third external electrode is L3, a length from a portion of the third external electrode farthest from the capacitor main body to a portion closer to the capacitor main body by about 40% of a thickness of the third external electrode in the laminating direction is L4, a ratio L4/L3 is about 80% or more.

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

A capacitor that includes a conductive porous substrate having a porous portion; a dielectric layer on the porous portion and containing an oxygen element and at least metal element; and an upper electrode on the dielectric layer. The porous portion has a path integral value of 1 m/m.sup.2 to 16 m/m.sup.2, and a porosity of 20% to 90%, and a ratio Z expressed by (1) below is 0.79 or more,

[00001]$\begin{array}{cc}Z=\frac{O_d/M_d}{O_r/M_r}& \left(1\right)\end{array}$

where O.sub.d and M.sub.d respectively represent signal intensities of the oxygen element and the metal element when the dielectric layer is analyzed by energy dispersive X-ray spectroscopy (EDS), and where O.sub.r and M.sub.r respectively represent signal intensities of the oxygen element and the metal element when a reference material having stoichiometric composition of the oxygen element and the at least one metal element constituting the dielectric layer is analyzed by the EDS.

A Z-directed capacitor according to one embodiment includes a body having top, bottom and side surfaces, a cross-sectional shape that is insertable into a mounting hole in a printed circuit board, and a plurality of stacked support members. Each support member includes an annular plate mounted on a surface thereof. A first conductive side channel and a second conductive side channel are formed in the side surface and extend along a top-to-bottom dimension of the body. A first set of the annular plates electrically contact the first conductive side channel but not the second conductive side channel and a second set of the annular plates electrically contact the second conductive side channel but not the first conductive side channel. A third conductive side channel is formed in the side surface, extends along the top-to-bottom dimension of the body and is electrically separated from the annular plates.

A multilayer ceramic capacitor includes a ceramic element body including internal electrodes therein. External electrodes are provided on end surfaces of the ceramic element body and electrically connected to exposed portions of respective ones of the internal electrodes. Each of the external electrodes includes a sintered metal layer, a conductive resin layer, and a plating layer. In a cross section including a first interface between the sintered metal layer and the conductive resin layer, the sintered metal layer includes a plurality of recesses each including an inlet extending along the first interface and an inner portion extending from the first interface into the sintered metal layer, each of the recesses having a shape in which a dimension of the inner portion is larger than a dimension of the inlet measured along the first interface, and in a cross section including a second interface between the conductive resin layer and the plating layer, a number of the metal particles exposed from the conductive resin layer in a portion of the second interface with a length of about 1 mm is 50 to 250.

A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO.sub.2 is deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuO.sub.2 and the dielectric metal oxide layer are annealed at a temperature below 500 C. The RuO.sub.2 in physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.

A monolithic ceramic electronic component having outer electrodes that include an inorganic substance containing at least Si, a crystal phase C containing at least Si, Ti, and Ba at the interfaces to a ceramic layer in peripheral end portions of the outer electrodes. A value of the crystal phase area ratio indicating the relationship between the area of the crystal phase C and the area of a glass phase G, which are formed at the interface to the ceramic layer, in a region within 5 m from the peripheral end portion of the outer electrode is within a range of 75% to 98%.

An electronic component includes: a chip having first and second end surfaces oriented in a direction of a first axis, first and second main surfaces oriented in a direction of a second axis orthogonal to the first axis, first and second side surfaces oriented in a direction of a third axis orthogonal to the first and second axes, and first and second external electrodes respectively covering the first and second end surfaces and each extending to the first and second main surfaces and side surfaces; a covering portion covering the chip from the first main surface toward the second main surface; and exposed portions provided to the second main surface, including regions where the first and second external electrodes are exposed without being covered with the covering portion, and being pushed out toward the first main surface along ridges connecting the first and second end surfaces and side surfaces.

A chip electronic component includes a body, in which a distance from a first surface to a second surface opposing with respect to the first surface is equal to or less than a distance from a third surface to a fourth surface opposing with respect to the third surface, a first internal electrode, and a second internal electrode exposed to the second surface of the body, and spaced apart from the third surface and the fourth surface of the body by a predetermined distance. A first corner protection portion is disposed on portions of surfaces adjacent to a first corner, where the first corner is a corner formed by the first surface, the third surface and the fifth surface of the body.