H01G7/00

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) VARIABLE CAPACITOR APPARATUSES AND RELATED METHODS
20170154734 · 2017-06-01 ·

Systems, devices, and methods for micro-electro-mechanical system (MEMS) tunable capacitors can include a fixed actuation electrode attached to a substrate, a fixed capacitive electrode attached to the substrate, and a movable component positioned above the substrate and movable with respect to the fixed actuation electrode and the fixed capacitive electrode. The movable component can include a movable actuation electrode positioned above the fixed actuation electrode and a movable capacitive electrode positioned above the fixed capacitive electrode. At least a portion of the movable capacitive electrode can be spaced apart from the fixed capacitive electrode by a first gap, and the movable actuation electrode can be spaced apart from the fixed actuation electrode by a second gap that is larger than the first gap.

ADJUSTABLE CAPACITOR AND ELECTRONIC APPARATUS

The present disclosure provides an adjustable capacitor and an electronic apparatus, and relates to the technical field of radio frequency device. The adjustable capacitor of the present disclosure includes a base substrate and at least one capacitor unit on the base substrate, each of the at least one capacitor unit includes a first plate, a second plate and a first connecting arm; the first plate and the connecting arm are on the base substrate; one end of the second plate is connected to the first connecting arm, the second plate and the first plate are opposite to each other, and a certain distance is between the second plate and the first plate.

Method of manufacturing capacitive micromachined ultrasonic transducer (CMUT)
12226799 · 2025-02-18 · ·

A method of manufacturing a capacitive micromachined ultrasonic transducer (CMUT) includes the steps of: a) forming a first dielectric layer on a first substrate; b) forming a second dielectric layer on a second substrate; c) forming a cavity in the first or second dielectric layer; d) assembling the first and second substrates by direct bonding of the surface of the second dielectric layer opposite to the second substrate to the surface of the first dielectric layer opposite to the first substrate; e) removing the second substrate to only keep above the cavity a suspended membrane formed by the second dielectric layer; and f) forming an upper electrode on the surface of the membrane opposite to the first substrate.

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Low passive inter-modulation capacitor
09660608 · 2017-05-23 · ·

A high power, low passive inter-modulation capacitor is presented, which is formed using metal clad substrates, which are broad-side coupled through a thin air gap. Each substrate may include metal layers affixed on both sides which are electrical coupled together to form a single capacitor plate, or each substrate may have only a single metal layer on the surface adjacent to the air gap. The capacitor has particular application in low cost RF and microwave filters, which may be used in communication equipment and communication test equipment such a diplexers, for low PIM applications.

Low passive inter-modulation capacitor
09660608 · 2017-05-23 · ·

A high power, low passive inter-modulation capacitor is presented, which is formed using metal clad substrates, which are broad-side coupled through a thin air gap. Each substrate may include metal layers affixed on both sides which are electrical coupled together to form a single capacitor plate, or each substrate may have only a single metal layer on the surface adjacent to the air gap. The capacitor has particular application in low cost RF and microwave filters, which may be used in communication equipment and communication test equipment such a diplexers, for low PIM applications.

CAPACITIVE HUMIDITY SENSOR
20170138882 · 2017-05-18 · ·

Provided is a capacitive humidity sensor. The capacitive humidity sensor includes an upper electrode disposed on a first plane, a plurality of first electrodes included in the upper electrode, a plurality of second electrodes disposed between the first electrodes, and a humidity sensitive layer surrounding the second electrodes.

Apparatus and methods for high voltage variable capacitor arrays with drift protection resistors
09634634 · 2017-04-25 · ·

Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Apparatus and methods for high voltage variable capacitor arrays with drift protection resistors
09634634 · 2017-04-25 · ·

Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.