An electron beam detection element according to an exemplary embodiment includes a plurality of unit cells. Each of the plurality of unit cells includes a diode of avalanche multiplication type and a plurality of memories. The diode of avalanche multiplication type is configured to detect an electron beam. The plurality of memories store signals of different frames respectively, each of the signals being output from the diode.

When using a charged particle beam aperture having a ring shape in a charged particle beam device, the charged particle beam with the highest current density immediately above the optical axis, among the charged particle beams is blocked, so that it is difficult to dispose the charged particle beam aperture at the optimal mounting position. Therefore, in addition to the ring-shaped charged particle beam aperture, a hole-shaped charged particle beam aperture is provided, and it is possible to switch between the case where the ring-shaped charged particle beam aperture is disposed on the optical axis of the charged particle beam and the case where the hole-shaped charged particle beam aperture is disposed on the optical axis of the charged particle beam.

A manufacturing method of a sample collection component, by which a removable light shielding component is disposed on a main body of the sample collection component to shield at least a portion of the light that passes through a storing space of the sample collection component.

A manufacturing method of a sample collection component, by which a removable light shielding component is disposed on a main body of the sample collection component to shield at least a portion of the light that passes through a storing space of the sample collection component.

An impedance adjustment device includes a variable capacitor unit. A microcomputer changes the capacitance value of the variable capacitor unit by switching on or off PIN diodes included in n capacitor circuits separately. Thus, the impedance on the plasma generator side when viewed from a high frequency power supply is adjusted. When changing the capacitance value of the variable capacitor unit to a target capacitance value, the microcomputer changes the capacitance value to a relay capacitance value different from the target capacitance value. The microcomputer changes the capacitance value to the target capacitance value after the capacitance value is changed to the relay capacitance value.

A method of patterning a substrate. The method may include providing a cavity in a layer, disposed on the substrate, the cavity having a first length along a first direction and a first width along a second direction, perpendicular to the first direction, and wherein the layer has a first height along a third direction, perpendicular to the first direction and the second direction. The method may include depositing a sacrificial layer over the cavity in a first deposition procedure; and directing angled ions to the cavity in a first exposure, wherein the cavity is etched, and wherein after the first exposure, the cavity has a second length along the first direction, greater than the first length, and wherein the cavity has a second width along the second direction, no greater than the first width.

An apparatus may include an exciter, disposed within a resonance chamber, to generate an RF power signal. The apparatus may include a resonator coil, disposed within the resonance chamber, to receive the RF power signal, and generate an RF output signal; and a pickup loop assembly, to receive the RF output signal and output a pickup voltage signal. The pickup loop assembly may include a pickup loop, disposed within the resonance chamber; and a variable attenuator, disposed at least partially between the resonator coil and the pickup loop. The variable attenuator may include a configurable portion, movable from a first position, attenuating a first amount of the RF output signal, to a second position, attenuating a second amount of the RF output signal, different from the first amount.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.