A method includes forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end spacing between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer.

A method includes forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end spacing between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

The invention provided an ion implantation system. The ion implantation system comprises an ion emitting device and a target plate device; the target plate device comprises a graphite electrode unit and a power supply unit; the graphite electrode unit is mounted on the lower end of a support frame, and the graphite electrode unit is a hollow structure; the graphite electrode unit comprises a graphite electrode and a hollow region I, the graphite electrode is connected to the power supply unit; the area of the hollow region I is smaller than that of the wafer to be processed, and the sum of the area of the graphite electrode and the area of the hollow region I is larger than an implantation area of the ion beam. When the ion beam is implanted to the wafer to be processed on a target plate for ion implantation, the power supply unit applies a voltage to the graphite electrode to generate an electric field in the opposite direction from the electric field generated by the ion beam motion, accordingly, the speed of the ion beam implanted to a location outside the wafer to be processed is reduced, and secondary contamination during ion implantation is avoided, so as to perform an ion implantation process more efficiently.

In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Provided are a thin film sample creation method and a charged particle beam apparatus capable of preventing a thin film sample piece from being damaged. The method includes a process of processing a sample by irradiating a surface of the sample with a focused ion beam (FIB) from a second direction that crosses a normal line to the surface of the sample to create a thin film sample piece and a connection portion positioned at and connected to one side of the thin film sample piece, a process of rotating the sample around the normal line, a process of connecting the thin film sample piece to a needle for holding the thin film sample piece, and a process of separating the thin film sample piece from the sample by irradiating the connection portion with a focused ion beam from a third direction that crosses the normal line.

A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

A measuring apparatus that irradiates a sample with a charged particle beam to observe the sample includes a particle source that outputs the charged particle beam, a lens that collects the charged particle beam, a detector that detects a signal of emitted electrons emitted from the sample which is irradiated with the charged particle beam, and a control device that controls the output of the charged particle beam and the detection of the signal of the emitted electrons in accordance with an observation condition, in which the control device sets, as the observation condition, a first parameter for controlling an irradiation cycle of the charged particle beam, a second parameter for controlling a pulse width of the pulsed charged particle beam, and a third parameter for controlling detection timing of the signal of the emitted electron within the irradiation time of the pulsed charged particle beam, and the third parameter is determined in accordance with a difference in intensity of signals of the plurality of the emitted electrons emitted from the irradiation position of the charged particle beam.