Patent classifications
H01L21/00
Graphene LHFETS (lateral heterostructure field effect transistors) on SI compatible with CMOS BEOL process
A field effect transistor includes a substrate, a passivation layer on the substrate forming a passivated substrate, wherein the passivation layer is inert to XeF.sub.2, and a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.
METHODS OF MANUFACTURING MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE
A method of manufacturing a magnetoresistive random-access memory (MRAM) device includes forming an insulating interlayer on a substrate, forming a contact plug extending through the insulating interlayer, forming a first blocking layer covering an upper surface of the contact plug, the first blocking layer including an amorphous material, forming a lower electrode layer on the first blocking layer, and forming a magnetic tunnel junction structure layer on the lower electrode layer.
Light emitting devices and components having improved chemical resistance and related methods
Light emitting devices and components having excellent chemical resistance and related methods are disclosed. In one embodiment, a component of a light emitting device can include a silver (Ag) portion, which can be silver on a substrate, and a protective layer disposed over the Ag portion. The protective layer can at least partially include an inorganic material for increasing the chemical resistance of the Ag portion.
Electrode for electrochemical sensors
An electrochemical electrode for use in a biosensor. The electrode comprises a substrate, a palladium metal layer manufactured on the substrate, and a palladium oxide-containing layer manufactured on the palladium metal layer. The palladium metal layer has a thickness of no more than 90 nm, and the palladium oxide-containing layer has a thickness of no more than 40 nm.
Packaged stackable electronic power device for surface mounting and circuit arrangement
A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
Dielectric member, structure, and substrate processing apparatus
A dielectric member that is attached to a lower surface of a stage is provided. The stage includes a base provided with a base channel through which a heat exchange medium passes. The dielectric member includes at least one first component including a passage that is connected to the base channel, and a second component surrounding the first component.
Using a laser to adjust at least one of a stage and a head unit during manufacturing of a display device
An apparatus for manufacturing a display device includes: a stage configured to hold a substrate; a movement unit configured to move relative to the stage; a head unit arranged on the movement unit and including a nozzle for discharging a liquid droplet onto the substrate; and a sensor unit configured to emit a laser to irradiate the liquid droplet falling from the head unit to the substrate to sense a portion of a planar shape of the liquid droplet. The apparatus is configured to control the movement unit or the head unit based on the sensed portion of the planar shape.
Semiconductor package including undermounted die with exposed backside metal
A semiconductor package includes a semiconductor die with an active surface and an inactive surface, the active surface including metal pillars providing electrical connections to functional circuitry of the semiconductor die, and a backside metal layer on the inactive surface. The backside metal layer is attached to the inactive surface. The semiconductor package further includes a plurality of leads with each of the leads including an internal leadfinger portion and an exposed portion that includes a bonding portion. Distal ends of the metal pillars are in contact with and electrically coupled to the internal leadfinger portions. The backside metal layer is exposed on an outer surface of the semiconductor package. The bonding portions and the backside metal layer approximately planar to each other.
Imaging system and imaging device
An imaging system according to the present disclosure includes: an imaging device that is mounted in a vehicle, and captures and generates an image of a peripheral region of the vehicle; and a processing device that is mounted in the vehicle, and executes processing related to a function of controlling the vehicle on the basis of the image. The imaging device includes: a first control line, a first voltage generator that applies a first voltage to the first control line, a first signal line, a plurality of pixels that applies a pixel voltage to the first signal line, a first dummy pixel that applies a voltage corresponding to the first voltage of the first control line to the first signal line in a first period, a converter including a first converter that performs AD conversion on the basis of a voltage of the first signal line in the first period to generate a first digital code, and a diagnosis section that performs diagnosis processing on the basis of the first digital code. The above-described processing device restricts the function of controlling the vehicle on the basis of a result of the diagnosis processing.
Method of manufacturing a semiconductor memory device
A semiconductor memory device, with which a manufacturing method is associated, includes a substrate. The semiconductor memory device also includes a source structure disposed on a first region of the substrate, memory cell strings connected to the source structure, and a capacitor structure disposed on a second region of the substrate. The capacitor structure is spaced apart from the source structure in a horizontal direction.