The present invention relates to various high quality n-type and p-type doped gallium-based semiconductor materials, electronic components incorporating these materials, and processes of producing these materials. In particular, The present invention relates processes to achieve high quality, uniform doping of a whole wafer or a thin layer of gallium-based semiconductor materials for various applications such as a vertical power transistor or diode.

In a method of forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers and one or more second nano layers positioned below the one or more first nano layers. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks, the one of more first nano layers into first nano-channels, and the one or more second nano layers into second nano-channels. The intermediate layers are recessed so that one or more first nano-channels of the first nano-channels and one or more second nano-channels of the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Bottom source/drain (S/D) regions are formed in the trenches to connect the second nano-channels. Top S/D regions are formed in the trenches to connect the first nano-channels.

A solder material may include nickel and tin. The nickel may include first and second amounts of particles. A sum of the particle amounts is a total amount of nickel or less. The first amount is between 5 at % and 60 at % of the total amount of nickel. The second amount is between 10 at % and 95 at % of the total amount of nickel. The particles of the first amount have a first size distribution, the particles of the second amount have a second size distribution, 30% to 70% of the first amount have a particle size in a range of about 5 μm around a particle size the highest number of particles have according to the first size distribution, and 30% to 70% of the second amount have a particle size in a range of about 5 μm around a particle size the highest number of particles have according to the second size distribution.

A wafer separating apparatus is provided which includes a wafer supporting member having an upper surface on which a bonded wafer formed of two wafers bonded with each other is placed; an arm portion arranged outside of the wafer supporting member, the arm portion being movable closer to and away from a bonded portion of the bonded portion of the bonded wafer supported by the supporting portion; and an inflating portion provided in an distal end portion of the arm portion, the inflating portion being inflatable in a direction intersecting the upper surface of the wafer supporting member.

A wiring substrate includes a first metal plate and a second electrode. The first metal plate includes a first electrode, a wiring, and a mount portion for an electronic component. The mount portion includes an upper surface of the wiring. The second electrode is joined to an upper surface of the first electrode. The first electrode is solid. The second electrode is solid.

An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures, a dielectric structure vertically extending partially through the stack structure, and a dielectric material vertically overlying and horizontally extending across the stack structure and the dielectric structure. Portions of at least the dielectric material and the dielectric structure are removed to form a trench vertically overlying and at least partially horizontally overlapping a remaining portion of the dielectric structure. The trench is substantially filled with additional dielectric material. Microelectronic devices, memory devices, and electronic systems are also described.

A device includes a dielectric layer, a conductive layer, electrode layers and an oxide semiconductor layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive layer is disposed on the first surface of the dielectric layer. The electrode layers are disposed on the second surface of the dielectric layer. The oxide semiconductor layer is disposed in between the second surface of the dielectric layer and the electrode layers, wherein the oxide semiconductor layer comprises a material represented by formula 1 (In.sub.xSn.sub.yTi.sub.zM.sub.mO.sub.n). In formula 1, 0<x<1, 0≤y<1, 0<z<1, 0<m<1, 0<n<1, and M represents at least one metal.

A die bonding method with corner or side contact without impact force includes the steps: picking up a die by a die bonding device, wherein a surface of the die has no solder and bump; moving the die to one side of a die placement area of a substrate, wherein the substrate has no solder and bump; blowing one corner or one side of the die a positive pressure from the die bonding device to bend the corner/side to contact the die placement area; forming a bonding wave after the corner/side of the die contacting the die placement area, and spreading the bonding wave from the corner/side to opposite corner/side of the die, and separating the die from the die bonding device gradually and bonding the die on the die placement area; and bonding the die on the die placement area completely.

A display device that can easily have high resolution is provided. A display device having both high display quality and high resolution is provided. A display device with high contrast is provided. A first EL film is deposited in contact with a top surface and a side surface of each of a first pixel electrode and a second pixel electrode each having a tapered shape. A first sacrificial film is formed to cover the first EL film. The first sacrificial film and the first EL film are etched to expose the second pixel electrode and form a first EL layer over the first pixel electrode and a first sacrificial layer over the first EL layer, and then, the first sacrificial layer is removed. The first EL film and the second EL film are etched by dry etching. The first sacrificial layer is removed by wet etching.