A process of detecting a thickness of a film layer to be processed or a depth of etching by using a result of detection of a signal indicating intensity of interference light having a plurality of wavelengths formed at a plurality of time instants from when plasma is formed to when the etching is completed. A start time instant is detected by using an amount of change in the intensity of the interference light. Then, a remaining film thickness or the etching amount at an arbitrary time instant is detected from a result of comparing actual data indicating the intensity of the interference light at the arbitrary time instant during the processing after the start time instant with a plurality of pieces of data for detection of the intensity of the interference light obtained in advance and associated with values of a the film thicknesses or the depths of etching.

A semiconductor manufacturing apparatus includes an imaging device that images a die; a lighting device having a light source that is a point light source or a line light source; and a controller configured to apply a light beam to a part of the die by the light source to form a bright field area on the die, and repeat moving the bright field area at a predetermined pitch and imaging of the die to inspect an inside of the bright field area.

A jig (30) includes a first block portion (100) at which a probe head (300) is installed, and a first suction port (112) formed on the first block portion (100). Air present on a side where one end of a probe (330) provided in the probe head (300) is located is sucked from the first suction port (112).

A circuit board has: an insulating substrate formed by plural ceramic insulating layers being layered on one another and having a first surface and a second surface on the opposite side to the first surface; a circuit conductor passing through the inside of the insulating substrate and positioned in a region from the first surface to the second surface; and at least one heating wire positioned in the insulating substrate. The heating wire is positioned in, among plural interlayer regions between the ceramic insulating layers, at least one interlayer region between the ceramic insulating layers and has a mesh shape having plural first through holes through which a portion of the circuit conductor passes and having plural second through holes through which the circuit conductor does not pass.

A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.

A micro light-emitting diode (μLED) chip includes a first electrode layer, a second semiconductor layer located on a surface of the first electrode layer, and a first semiconductor layer located on a side of the second semiconductor layer away from the first electrode layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer. The second semiconductor is electrically connected to the first electrode layer, and is configured to transmit first carriers. The first semiconductor layer is configured to transmit second carriers. The light-emitting layer is configured to be excited to emit light upon combination of the first carriers and the second carriers. A surface of the first semiconductor layer away from the light-emitting layer is a concave-convex microstructure, and convex portions of the concave-convex microstructure are configured to receive an electron beam.

Method for searching a hole pattern in image includes extracting, from an image where a hole pattern is formed, plural outline position candidates serving as candidates for plural positions where an outline of the hole pattern passes, generating, for each pixel in a region including the plural outline position candidates, a distance map which defines, for each of plural directions, a distance from each of the plural outline position candidates to each of pixels arrayed in a target direction of the plural directions, extracting a candidate for a center pixel of the hole pattern by using the distance map generated for each direction, and searching, in the plural outline position candidates, a group of outline position candidates which satisfies a predetermined condition in the case of using the candidate for the center pixel as a starting point, as plural outline positions where the outline of the hole pattern passes.

A silicon carbide epitaxial substrate according to a present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer disposed on the silicon carbide substrate. The silicon carbide epitaxial layer includes a boundary surface in contact with the silicon carbide substrate and a main surface opposite to the boundary surface. The main surface has an outer circumferential edge, an outer circumferential region extending within 5 mm from the outer circumferential edge, and a central region surrounded by the outer circumferential region. When an area density of double Shockley stacking faults in the outer circumferential region is defined as a first area density, and an area density of double Shockley stacking faults in the central region is defined as a second area density, the first area density is five or more times as large as the second area density, the second area density is 0.2 cm.sup.−2 or more.

The present application relates to a test circuit, comprising: M stages of test units, first terminals of test units in each stage being all connected to a power wire, second terminals of test units in each stage being all connected to a ground wire, third terminals of test units in the first stage being connected to the power wire, and third terminals of test units in the i.sup.th stage being connected to fourth terminals of test units in the (i−1).sup.th stage; wherein, the M and i are positive integers greater than or equal to 2.

The present application relates to a test circuit, comprising: M test units, each test unit having a first terminal and a second terminal, a first terminal of each test unit being connected to a power wire, a second terminal of each test unit being connected to a ground wire, M being a positive integer; each test unit comprises a TDDB test component, a switch, and a control circuit; the TDDB test component has a first equivalent resistance before being broken down, the TDDB test component has a second equivalent resistance after being broken down, and the first equivalent resistance is greater than the second equivalent resistance.