According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

A probe card includes: a plurality of conductive contact probes; a probe head configured to accommodate ends of the plurality of contact probes; a laminated member laminated on the probe head on a side opposite to a side of the probe head; and a fastening member including a screw and a nut configured to fasten the probe head and the laminated member to each other, the screw including a head provided on the side of the probe head in which the contact probes extend outwardly, and a shaft inserted through the probe head and the laminated member, the shaft extending and having a diameter smaller than a diameter of the head. The shaft is fixed to the probe head, is threadedly connected to the nut on an end side opposite to the head side, and is configured to fasten the probe head and the laminated member to each other.

This mounting apparatus is provided with: a plurality of bonding stations each comprising a bonding apparatus for bonding a semiconductor chip onto a substrate wafer, and a chip supply apparatus for supplying the semiconductor chip to the bonding apparatus; and a single wafer transfer apparatus which transfers the substrate wafer in order to supply the substrate wafer to each of the plurality of bonding stations and to collect the substrate wafer from each of the plurality of bonding stations.

A machine station file processing method includes: monitoring operation of a file system of a machine station server and acquiring a transaction file generated by the operation, the transaction file comprising transaction data; converting a format of the transaction data according to preset warehousing rules to generate model-layer data; and sending, to a data warehouse server, the model-layer data and a data analysis request, the data analysis request is used to instruct the data warehouse server to acquire application-layer data according to the model-layer data.

The present disclosure provides a wafer sample analysis method and device. The method is applied to a secondary-ion-mass spectroscope (Sims) and includes: providing a wafer sample, the wafer sample at least including a slope configured to expose a substrate, a first protective layer and a first doped layer on a same surface, the first protective layer being formed on the substrate, and the first doped layer being formed on the first protective layer; and acquiring and analyzing a slope image of the slope to obtain a doping depth and a doping concentration of elements in the wafer sample in the slope image.

The present invention relates to a picker device. The pickers are arranged in a line on a picker support, and each of the pickers comprises: a main nozzle in which vacuum pressure is applied or released at the lower end; and a lift actuator supported by the picker support to lift and lower the main nozzle. A sub-nozzle docking module is docked or undocked with the main nozzles, and comprises: at least one sub-nozzle which adsorbs or desorbs an object to be transferred as vacuum pressure is applied or released at the lower end thereof; a docking mount which receives vacuum pressure from the main nozzles in a docked state with the main nozzles by supporting the sub-nozzle at the lower end thereof and delivers the vacuum pressure to the sub-nozzle through a vacuum passage; and an attachment/detachment mechanism for attaching and detaching the docking mount to and from the picker support.

A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.

Embodiments of the present application relate to the technical field of semiconductor, and disclose a design method of a wafer layout and an exposure system of a lithography machine. The design method of a wafer layout includes: providing a yield distribution map of a wafer under an initial wafer layout; determining a yield edge position of the wafer according to the yield distribution map; and calculating a new wafer layout according to a die size and the yield edge position.

An inspection jig includes a rod-shaped probe, a first support portion that supports one end portion side of the probe, a second support portion that supports the other end portion side of the probe, and a separation holding member that holds the first support portion and the second support portion to be separated from each other. The first support portion includes a support plate in which a through hole through which the probe is inserted is formed. A reinforcing plate having bending strength stronger than that of the support plate is disposed on a surface of the support plate facing the second support portion.

A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.