A semiconductor device includes a semiconductor die having a first side having a first terminal and an opposite second side having at least two second terminals. A lead frame has a first part and a second part. The second part of the lead frame is both electrically and mechanically spaced from the first part. The second side of the die is attached to the lead frame such that the first and second lead frame parts are respectively connected to the at least two second terminals. The first and second lead frame parts include respective first and second extensions that project past a side of the die and provide first and second terminal surfaces that are co-planar with the first terminal on the first side of the die. The device makes use of the terminals on the both sides of the die. The device second side is exposed for thermal performance.

Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

A method for manufacturing a semiconductor device includes forming a first stacked body having a plurality of first material films and a plurality of second material films that are alternately stacked, in a divided region of a semiconductor wafer including a chip region in which a semiconductor element is provided and the divided region between the adjacent chip regions, a plurality of times in a normal line direction of a substrate surface of the semiconductor wafer. The semiconductor wafer is fragmented by a blade having a width wider than the width of the first stacked body.

A semiconductor package includes a chip, a layer which is thermally coupled to the chip and which is formed from a material having a triggering temperature of greater than or equal to 200° C., starting from which an exothermic reaction takes place, and encapsulating material which at least partly covers the chip and the layer. The layer is configured in such a way and is arranged relative to the chip in such a way that, in the case of a triggered exothermic reaction of the material of the layer, at least one component of the chip is damaged on account of the temperature increase caused by the exothermic reaction.

A method of manufacturing a light source device includes: disposing bumps containing a first metal on a first substrate which is thermally conductive; disposing a bonding member on the bumps, the bonding member containing Au—Sn alloy; disposing a light emitting element on the bumps and the bonding member; and heating the first substrate equipped with the bumps, the bonding member, and the light emitting element.

A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.

Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes providing an integrated circuit die having contacts disposed thereon, forming an insulating material over the integrated circuit die and the contacts, and forming an opening in the insulating material over the contacts. A eutectic material is formed in the openings over the contacts, and the integrated circuit die is electrically tested by contacting the eutectic material disposed over the contacts. The eutectic material is removed.

An electrical component is disclosed, wherein the electrical component comprises: a body; a conductive element disposed in the body, wherein at least one portion of a terminal part of the conductive element is exposed outside of the body; a metal foil having an adhesive material on the bottom surface thereof, the metal foil being adhered on the body through the adhesive material and covering a first portion of the terminal part of the conductive element, wherein a second portion of the terminal part of the conductive element is not covered by the metal foil; and a metal layer, overlaying on the metal foil and covering the second portion of the terminal part of the conductive element, wherein the metal layer is electrically connected to the second portion of the terminal part of the conductive element for electrically connecting with an external circuit.

A semiconductor integrated circuit device includes a fuse element that can be laser trimmed to adjust the characteristics of the semiconductor integrated circuit device, The semiconductor integrated circuit device includes an interlayer insulating film above the fuse element, and the thickness of the interlayer insulating film is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The laser trimming processing is thus stabilized without needing a high level of dry etching stabilization control.