An embodiment related to a device. The device includes a first die with first and second die surfaces. The second die surface is bonded to a first die attach pad (DAP) disposed on a first substrate surface of a package substrate and the first die surface includes a first die contact pad. The device also includes a first clip bond including a first clip bond horizontal planar portion attached to the first die contact pad on the first die surface, and a first clip bond vertical portion disposed on an edge of the first clip bond horizontal planar portion. The first clip bond vertical portion is attached to a first substrate bond pad on the first substrate surface. The device further includes a first conductive clip-die bonding layer with spacers on the first die contact pad of the first die. The first conductive clip-die bonding layer bonds the first clip bond horizontal planar portion to the first die contact pad, and the spacers maintain a uniform Bond Line Thickness (BLT) of the first conductive clip-die bonding layer.

A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.

A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

A display device and a manufacturing method thereof are provided. The display device includes: a first array substrate, a first opposite substrate, a second array substrate and a second opposite substrate stacked in sequence; the first array substrate comprises a first overlap portion overlapping with the first opposite substrate, a first extension portion extending from the first overlap portion, and the second array substrate comprises a second overlap portion overlapping with the second opposite substrate, a second extension portion extending from the second overlap portion; a side, facing the second extension portion, of the first extension portion comprises a first control IC, and a side, away from the first extension portion, of the second extension portion comprises a second control IC; and a space between the first and the second extension portions is filled with a heat dissipation component at least in an area where the first control IC is.

An electronic package including a middle patterned conductive layer, a first redistribution circuitry disposed on a first surface of the middle patterned conductive layer and a second redistribution circuitry disposed on a second surface of the middle patterned conductive layer is provided. The middle patterned conductive layer has a plurality of middle conductive pads. The first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements. Each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section. The second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements. Each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include at least two integrated circuit dies that communicate using an embedded multi-die interconnect bridge (EMIB) in a substrate of the multi-chip package. The EMIB may receive power at contact pads formed at a back side of the EMIB that are coupled to a back side conductor on which the EMIB is mounted. The back side conductor may be separated into multiple regions that are electrically isolated from one another and that each receive a different power supply voltage signal or data signal from a printed circuit board. These power supply voltage signals and data signals may be provided to the two integrated circuit dies through internal microvias or through-silicon vias formed in the EMIB.

In certain embodiments, a method for designing a semiconductor device includes generating a 2D design for fabricating chiplets on a substrate. The chiplets are component levels for a multi-chip integrated circuit. The 2D design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The first and second chiplets are adjacent on the substrate. The second layout is a mirror image of the first layout across a reference line shared by the first and second chiplets. The first surfaces of the first and second chiplets are both either top or bottom surfaces. The method further includes generating one or more photomasks according to the design.