A pixel array including an Si.sub.xGe.sub.y layer disposed on a first semiconductor layer. A plurality of pixels is disposed in the first semiconductor layer. The plurality of pixels includes: (1) a first portion of pixels separated from the Si.sub.xGe.sub.y layer by a spacer region and (2) a second portion of pixels including a first doped region in contact with the Si.sub.xGe.sub.y layer. The pixel array also includes pinning wells disposed between individual pixels in the plurality of pixels. A first portion of the pinning wells extend through the first semiconductor layer. A second portion of the pinning wells extend through the first semiconductor layer and the Si.sub.xGe.sub.y layer.

Fully integrated, on-chip DC-DC power converters are provided. In one aspect, a DC-DC power converter includes: a SOI wafer having a SOI layer separated from a substrate by a buried insulator, wherein the SOI layer and the buried insulator are selectively removed from at least one first portion of the SOI wafer, and wherein the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; at least one GaN transistor formed on the substrate in the first portion of the SOI wafer; at least one CMOS transistor formed on the SOI layer in the second portion of the SOI wafer; a dielectric covering the GaN and CMOS transistors; and at least one magnetic inductor formed on the dielectric. A method of forming a fully integrated DC-DC power converter is also provided.

A selector device for a memory cell in a memory array may include a first electrode, and a separator that include a first region of a single-composition layer of a mixed ionic-electronic conduction material with a first concentration of defects; and a second region of a single-composition layer of a transitional metal oxide with a second concentration of defects that is different from the first concentration of defects. The selector device may also include a second electrode, where the separator is between the first electrode and the second electrode.

The present disclosure provides a manufacturing method of a display backplane which includes a base substrate having first, second and third portions. The manufacturing method includes: forming a flexible layer extending from the first portion to and covering the second and third portions; forming a pixel driving circuit on the first portion and a backlight circuit on the third portion, wherein a part of a film layer of the pixel driving circuit extends from the first portion to and covers the second and third portions; removing a film layer on a side of the flexible layer away from the base substrate and on the second portion; separating the flexible layer from the second and third portions; removing the second and third portions; and bending a film layer separated from the third portion to a side of the first portion away from the flexible layer.

There are disclosed impedance matching networks and technique for impedance matching to microwave power transistors. Distributed capacitor inductor networks are used so as to provide a high degree of control and accuracy, especially in terms of inductance values, in comparison to existing lumped capacitor arrangements. The use of bond wires is reduced, with inductance being provided primarily by microstrip transmission lines on the capacitors.

A semiconductor structure includes a layered dipole structure formed upon a fin sidewall within a fin trench. The layered dipole structure includes a dipole layer of opposite polarity relative to the polarity of the fin and reduces source to drain leakage. A semiconductor structure may include a first layered dipole structure formed within a gate trench within a first polarity region of the semiconductor structure. A second layered dipole structure is formed within a gate trench within a second polarity region of the semiconductor structure and formed upon the first layered dipole structure. The layered dipole structure nearest to the bottom of the gate trench includes a dipole layer of opposite polarity relative to the polarity region of the semiconductor structure where the gate trench is located and reduces source to drain leakage.

A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

The invention relates to a photonic component (1) having at least one semiconductor laser amplifier (200), which has at least one first mirror surface (210a) for coupling and/or decoupling optical radiation (S). The first mirror surface (210a) of the semiconductor laser amplifier (200) is coupled to a photonically integrated chip (100), wherein the chip (100) is arranged such that the chip can emit optical radiation (S) from the chip top side (O100) thereof in the direction of the first mirror surface (210a) and couple said radiation in the semiconductor laser amplifier (200), and wherein the emitting of the radiation (S) away from the chip top side (O100) occurs in the direction of the first mirror surface (210a) at an angle of 90°±20°, in particular perpendicular, to the chip top side (O100).

The invention relates to a photonic component (1) having at least one semiconductor laser amplifier (200), which has at least one first mirror surface (210a) for coupling and/or decoupling optical radiation (S). The first mirror surface (210a) of the semiconductor laser amplifier (200) is coupled to a photonically integrated chip (100), wherein the chip (100) is arranged such that the chip can emit optical radiation (S) from the chip top side (O100) thereof in the direction of the first mirror surface (210a) and couple said radiation in the semiconductor laser amplifier (200), and wherein the emitting of the radiation (S) away from the chip top side (O100) occurs in the direction of the first mirror surface (210a) at an angle of 90°±20°, in particular perpendicular, to the chip top side (O100).

One embodiment provides an imaging apparatus including a photoelectric conversion unit; and a junction type field effect transistor configured to output a signal based on a carrier generated by the photoelectric conversion unit. The junction type field effect transistor includes a semiconductor region of a first conductivity type that forms a channel and a gate region of a second conductivity type. The semiconductor region of the first conductivity type includes a first region and a second region. The first region and the second region are disposed in this order toward a direction to which a carrier in the channel drifts. An impurity density of the second region is lower than an impurity density of the first region.