A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.

The present technology relates to a solid-state image capturing apparatus and an electronic device that can acquire a normal image and a narrow band image at the same time. The solid-state image capturing apparatus includes a plurality of substrates laminated in two or more layers, and two or more substrates of the plurality of substrates have pixels that perform photoelectric conversion. At least one substrate of the substrates having the pixels is a visible light sensor that receives visible light, and at least another substrate of the substrates having the pixels is a narrow band light sensor that includes narrow band filters being optical filters permeating light in a narrow wavelength band, and receives narrow band light in the narrow band.

In one embodiment, a device includes a first sheet configured to flex; a second sheet disposed below the first sheet; and an intermediate region disposed between the sheets. The intermediate region may include multiple supports, each of the supports connected to portions of the first and second sheets and configured to maintain a spacing between the sheets. The intermediate region may also include multiple channels configured to contain a fluid in the spacing between the sheets, each of the channels disposed between two or more supports. The fluid is configured to be in an active or an inactive state. When the fluid is in the inactive state, the device is substantially flexible, and when the fluid is in the active state, the device is substantially rigid.

In one embodiment, a device includes a first sheet configured to flex; a second sheet disposed below the first sheet; and an intermediate region disposed between the sheets. The intermediate region may include multiple supports, each of the supports connected to portions of the first and second sheets and configured to maintain a spacing between the sheets. The intermediate region may also include multiple channels configured to contain a fluid in the spacing between the sheets, each of the channels disposed between two or more supports. The fluid is configured to be in an active or an inactive state. When the fluid is in the inactive state, the device is substantially flexible, and when the fluid is in the active state, the device is substantially rigid.

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

A CMOS image sensor has an image array as a matrix of unit pixels each including at least a photodiode, a memory for holding a charge stored in the photodiode, a floating diffusion region for converting the charge in the memory into a voltage, a first transfer gate for transferring the charge from the photodiode to the memory, a second transfer gate for transferring the charge from the memory to the floating diffusion region, and a resetting transistor for resetting the charge in the floating diffusion region. The unit pixels are driven to set the potential of a potential barrier at a boundary between the memory and the floating diffusion region to a potential such that a charge overflowing the memory is transferred to the floating diffusion region, when the first transfer gate is turned on. The CMOS image sensor operates in a global shutter mode for capturing moving images.

The present disclosure relates to a display device, an array substrate and a manufacturing method thereof, and relates to the technical field of display. The method includes steps of: providing a base substrate, and forming a semiconductor pattern, a gate insulation layer, a gate electrode, an insulation layer and a source/drain electrode on the base substrate, and further includes forming the composite material layer on the base substrate including the semiconductor pattern, and hydrotreating the composite material layer, in which the composite material layer may contain titanium complex-graphene oxide. The present disclosure is capable of omitting the interlayer insulation layer, thereby avoiding the situation that a flexible layer cannot be displayed due to the breakage of insulation layer between inorganic layers, thereby improving bending performance of the flexible screen.

A method includes receiving a precursor having a substrate and first and second pluralities of gate structures, the first pluralities having a greater pitch than the second pluralities. The method further includes depositing a dielectric layer covering the substrate and the first and second pluralities; and performing an etching process to the dielectric layer. The etching process removes a first portion of the dielectric layer over the substrate, while a second portion of the dielectric layer remains over sidewalls of the first and second pluralities. The second portion of the dielectric layer is thicker over the sidewalls of the second plurality than over the sidewalls of the first plurality. The method further includes etching the substrate to form third and fourth pluralities of recesses adjacent the first and second pluralities, respectively; and epitaxially growing fifth and sixth pluralities of semiconductor features in the third and fourth pluralities, respectively.

An array substrate, a method for manufacturing the same and a display device are provided. The method includes: providing a base substrate; forming a conductive material thin film on the base substrate; forming a first photoresist layer on a side of the conductive material thin film distal to the base substrate; etching the conductive material thin film by using the first photoresist layer as a mask to obtain a first etched pattern; removing third covering portions of the first photoresist layer to obtain a second photoresist layer; and etching the first etched pattern by using the second photoresist layer as a mask to obtain a gate electrode and a signal line.

One object is to provide a semiconductor device with a structure which enables reduction in parasitic capacitance sufficiently between wirings. In a bottom-gate type thin film transistor including a stacked layer of a first layer which is a metal thin film oxidized partly or entirely and an oxide semiconductor layer, the following oxide insulating layers are formed together: an oxide insulating layer serving as a channel protective layer which is over and in contact with a part of the oxide semiconductor layer overlapping with a gate electrode layer; and an oxide insulating layer which covers a peripheral portion and a side surface of the stacked oxide semiconductor layer.