A semiconductor device is fabricated by a method including the following steps: a first step of forming a semiconductor film containing a metal oxide over an insulating layer; a second step of forming a conductive film over the semiconductor film; a third step of forming a first resist mask over the conductive film and etching the conductive film to form a first conductive layer and to expose a top surface of the semiconductor film that is not covered with the first conductive layer; and a fourth step of forming a second resist mask that covers a top surface and a side surface of the first conductive layer and part of the top surface of the semiconductor film and etching the semiconductor film to form a semiconductor layer and to expose a top surface of the insulating layer that is not covered with the semiconductor layer.

A TFT includes an oxide semiconductor layer including a conductive region electrically connected to a source electrode, a conductive region electrically connected to a drain electrode, a channel region being an oxide semiconductor region that overlaps a gate electrode, and at least one resistive region being an oxide semiconductor region provided between the channel region and a conductive region adjacent to the channel region.

A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.

An organic light-emitting diode includes: a first electrode, a light-emitting stack thereon including: a hole transport layer (HTL), a blue light-emitting layer including: a blue host material (BHM), and a blue fluorescent dopant (BFD) material, and an electron transport layer (ETL), and a second electrode on the light-emitting stack, wherein BFD LUMO>BHM, BFD HOMO>BHM, BFD singlet energy <BHM, HTL HOMO>BHM and BFD, HTL HOMO−BFD HOMO≤0.1 eV, the HTL material LUMO>the BHM, HTL LUMO−BHM LUMO>0.5 eV, HTL LUMO>BFD, ETL LUMO>BHM and BFD, a difference in LUMO between the ETL material and the BFD material ≤0.1 eV, and the HTL material, the ETL material, and the BHM have the following triplet energy relationships: T.sub.1,BH<T.sub.1,HTL and T.sub.1,BH<T.sub.1,ETL, 2.8<T.sub.1,HTL<3.0, and 2.6<T.sub.1,ETL<2.8.

A thin-film transistor substrate includes an insulating substrate, a first insulating layer, a first thin-film transistor including a first oxide semiconductor film, a second insulating layer located upper than the first insulating layer, and a second thin-film transistor including a second oxide semiconductor film different in composition from the first oxide semiconductor film. At least a part of the first oxide semiconductor film is provided above and in contact with the first insulating layer. The first insulating layer is the uppermost insulating layer among insulating layers located lower than and in contact with the first oxide semiconductor film. At least a part of the second oxide semiconductor film is provided above and in contact with the second insulating layer. The second insulating layer is the uppermost insulating layer among insulating layers located lower than and in contact with the second oxide semiconductor film.

To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device includes: a first semiconductor substrate; and a second semiconductor substrate. The first semiconductor substrate is provided with a first electrode including a first protruding portion and a first base portion. The first protruding portion includes a first abutting surface. The first base portion is linked to the first protruding portion and has volume greater than volume of the first protruding portion. The second semiconductor substrate is provided with a second electrode including a second protruding portion and a second base portion. The second protruding portion includes a second abutting surface that abuts the first abutting surface. The second base portion is linked to the second protruding portion and has volume greater than volume of the second protruding portion. The second semiconductor substrate is stacked on the first semiconductor substrate.

An imaging unit according to an embodiment of the present disclosure includes: a first substrate; a second substrate; and a wiring line. The first substrate includes a sensor pixel on a first semiconductor substrate. The sensor pixel performs photoelectric conversion. The second substrate includes a readout circuit on a second semiconductor substrate. The readout circuit outputs a pixel signal based on electric charge outputted from the sensor pixel. The second substrate is stacked on the first substrate. The wiring line extends between the first semiconductor substrate and the second semiconductor substrate in a direction parallel with the first semiconductor substrate. The wiring line at least partially has a stack region in which a semiconductor layer and a metal layer are stacked.

Provided is a semiconductor device with a wiring layer including a plurality of wiring lines extending in a first direction; a first insulating film stacked on the wiring layer that has a gap region between the plurality of wiring lines adjacent to each other in a second direction; and a second insulating film between the plurality of wiring lines and the first insulating film. Each wiring line includes a metal film and a barrier metal layer. The metal film includes an electrically conductive material including a first metal. The barrier metal layer partially covers surroundings of the metal film in a cross section orthogonal to the first direction and includes a material including a second metal. The second metal prevents diffusion of the first metal. The second insulating film includes an insulating material and covers a portion of the metal film. The insulating material prevents diffusion of the first metal.

Electrical connection between mutually facing electrodes is provided. A solid-state imaging device includes: a first semiconductor base; a second semiconductor base bonded to the first semiconductor base; and a conductive polymer, the first semiconductor base including a first semiconductor layer in which a photoelectric conversion unit is provided, a first multilayer wiring layer stacked on the first semiconductor layer, and a first metal pad formed on a surface of the first multilayer wiring layer on a side opposite to the first semiconductor layer, the second semiconductor base including a second semiconductor layer in which an active element is provided, a second multilayer wiring layer stacked on the second semiconductor layer, and a second metal pad on a surface of the second multilayer wiring layer on a side opposite to the second semiconductor layer, the conductive polymer electrically connecting the first metal pad and to the second metal pad.

Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.