A semiconductor memory device includes first conducting layers and a first semiconductor layer opposed to the first conducting layers. If a concentration of the dopant in the first semiconductor layer is measured along an imaginary straight line, the concentration of the dopant has: a maximum value at a first point, a minimum value in a region closer to the first conducting layer than the first point at a second point; and a minimum value in a region farther from the first conducting layer than the first point at a third point. The second point is nearer to an end portion of the first semiconductor layer on the first conducting layer side than that on the opposite side. The third point is farther from the end portion on the first conducting layer side than that on the opposite side.

A liquid crystal display device with a high aperture ratio is provided. A liquid crystal display device with low power consumption is provided. A display device includes a transistor and a capacitor. The transistor includes a first insulating layer, a first semiconductor layer in contact with the first insulating layer, a second insulating layer in contact with the first semiconductor layer, and a first conductive layer electrically connected to the first semiconductor layer via an opening portion provided in the second insulating layer. The capacitor includes a second conductive layer in contact with the first insulating layer, the second insulating layer in contact with the second conductive layer, and the first conductive layer in contact with the second insulating layer. The second conductive layer includes a composition similar to that of the first semiconductor layer. The first conductive layer and the second conductive layer are configured to transmit visible light.

A method of fabricating an array substrate is provided. The method includes forming a plurality of first thin film transistors on a base substrate, a respective one of the plurality of first thin film transistors formed to include a first active layer, a first gate electrode, a first source electrode and a first drain electrode; and forming a plurality of second thin film transistors on the base substrate, a respective one of the plurality of second thin film transistors formed to include a second active layer, a second gate electrode, a second source electrode and a second drain electrode. Forming the first source electrode includes forming a first source sub-layer and forming a second source sub-layer in separate patterning steps. Forming the first drain electrode includes forming a first drain sub-layer and forming a second drain sub-layer in separate patterning steps.

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure including two parallel barrier walls extending vertically through the alternating layer stack and laterally along a word line direction to laterally separate the first region from the second region. The memory device further comprises a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack.

A display device, a method for controlling the same, and a display panel are provided, the display device includes: a transparent substrate; a plurality of electroluminescent devices arranged in an array on the substrate, a device with variable transmittance located between the electroluminescent devices and the substrate, the device with variable transmittance is configured so that a transmittance of the device with variable transmittance is switchable between a first transmittance and a second transmittance, and the first transmittance is greater than the second transmittance; and an image acquisition device on a side of the substrate away from the electroluminescent devices, in a case where the transmittance of the device with variable transmittance is switched to the first transmittance, external light irradiating the display device can pass through the device with variable transmittance and be incident on the image acquisition device.

A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

There is provided a semiconductor device in which the inter-wiring capacitance of wiring lines provided in any layout is further reduced. A semiconductor device (1) including: a first inter-wiring insulating layer (120) that is provided on a substrate (100) and includes a recess on a side opposite to the substrate; a first wiring layer (130) that is provided inside the recess in the first inter-wiring insulating layer; a sealing film (140) that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer; a second inter-wiring insulating layer (220) that is provided on the first inter-wiring insulating layer to cover the recess; and a gap (150) that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.

A method includes forming a plurality of openings extending into a substrate from a front surface of the substrate. The substrate includes a first semiconductor material. Each of the plurality of openings has a curve-based bottom surface. The method includes filling the plurality of openings with a second semiconductor material. The second semiconductor material is different from the first semiconductor material. The method includes forming a plurality of pixels that are configured to sense light in the plurality of openings, respectively, using the second semiconductor material.

A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

A display device may include a first gate electrode disposed on a substrate, a buffer layer disposed on the first gate electrode, a first active pattern on the buffer layer, the first active pattern overlapping the first gate electrode and including an oxide semiconductor, a second active pattern on the buffer layer, spaced apart from the first active pattern, and including an oxide semiconductor, the second active pattern including a channel region, and a source region and a drain region, a source pattern and a drain pattern respectively at ends of the first active pattern, a first insulation pattern disposed on the first active pattern, a second insulation pattern disposed on the channel region, a first oxygen supply pattern on the first insulation pattern, a second oxygen supply pattern on the second insulation pattern, and a second gate electrode on the second oxygen supply pattern.