A semiconductor device according to one embodiment is provided with: a substrate; a stacked body provided on the substrate; and a pillar portion penetrating the stacked body. The pillar portion has a first film including a first material and a second material, and a second film provided on an inner side of the first film. The second material is a material that increases an etching rate of the first material as a composition rate relative to the first material is higher, and the composition rate gradually decreases from an upper part to a lower part of the first film.

A thin film transistor (TFT) array substrate for an electronic device includes a first active layer of a first TFT which is an oxide semiconductor layer including molybdenum, a second active layer of a second TFT which is an oxide semiconductor layer and disposed on a buffer layer to be spaced apart from the first active layer of the first TFT, a first gate insulating film overlapping the first active layer and the second active layer, a first gate electrode of the first TFT overlapping the first gate insulating film and a part of the first active layer, and a second gate electrode of the second TFT overlapping the first gate insulating film, spaced apart from the first gate electrode, and overlapping a part of the second active layer. Accordingly, the first TFT has a high subthreshold parameter, and the second TFT has high mobility.

Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

A semiconductor device has laminated therein three or more chips. The plurality of chips are provided with substrates, transmission coils, and reception coils that are disposed in regions where the transmission coils and the reception coils do not overlap with each other in an in-plane direction of the substrates. The transmission coils are disposed in regions that are in a lamination direction and that are adjacent to and overlap with reception coils of other chips. The reception coils are configured to allow data transmission with respect to the transmission coils that are disposed on the same substrates.

An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

An image sensor is provided and includes a photoelectric conversion layer, an integrated circuit layer, and a charge storage layer. The photoelectric conversion layer includes a pixel separation structure defining pixel regions, each including a photoelectric conversion region. The integrated circuit layer read charges from the photoelectric conversion regions. The charge storage layer includes a stacked capacitor for each of the pixel regions. The stacked capacitor includes a lower pad electrode, an intermediate pad electrode, an upper pad electrode, a contact plug connecting the upper pad electrode to the lower pad electrode, a first lower capacitor structure connected between the lower pad electrode and the intermediate pad electrode, and an upper capacitor structure connected between the intermediate pad electrode and the upper pad electrode. The upper capacitor structure is stacked on the lower capacitor structure to partially overlap the lower capacitor structure when viewed in plan view.

A semiconductor storage device includes a substrate. A stacked body is disposed above the substrate and has an alternately stacked plurality of first insulating layers and plurality of conductive layers. A plurality of columnar portions penetrate the stacked body and include a core layer disposed at a center portion of the columnar portions, a semiconductor layer provided around the core layer, and a memory film disposed around the semiconductor layer. A slit divides an upper conductive layer at an upper portion of the stacked body. In a columnar portion overlapping the slit, the core layer or the memory film protrudes from the semiconductor layer.

The present disclosure discloses an oxide semiconductor thin-film transistor and a method of fabricating the same. According to one embodiment of the present disclosure, the oxide semiconductor thin-film transistor includes a substrate, a gate electrode, a gate insulating layer, an oxide semiconductor layer, and source and drain electrodes. Since the gate insulating layer is formed of at least one of zirconium oxide (ZrOx) and lanthanum zirconium oxide (LaZrOx), the electrical characteristics of the oxide semiconductor thin-film transistor may be controlled by the gate insulating layer.

It is recognized that, because of its unique properties, graphene can serve as an interface with biological cells that communicate by an electrical impulse, or action potential. Responding to a sensed signal can be accomplished by coupling a graphene sensor to a low power digital electronic switch that is activatable by the sensed low power electrical signals. It is further recognized that low power devices such as tunneling diodes and TFETs are suitable for use in such biological applications in conjunction with graphene sensors. While tunneling diodes can be used in diagnostic applications, TFETs, which are three-terminal devices, further permit controlling the voltage on one cell according to signals received by other cells. Thus, by the use of a biological sensor system that includes graphene nanowire sensors coupled to a TFET, charge can be redistributed among different biological cells, potentially with therapeutic effects.

A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.