A silicon photomultiplier includes a plurality of microcells providing a pulse output in response to an incident radiation, each microcell including circuitry configured to enable and disable the pulse output. Each microcell includes a cell disable switch. The control logic circuit controls the cell disable switch and a self-test circuit. A microcell's pulse output is disabled when the cell disable switch is in a first state. A method for self-test calibration of microcells includes providing a test enable signal to the microcells, integrating dark current for a predetermined time period, comparing the integrated dark current to a predetermined threshold level, and providing a signal if above the predetermined threshold level.

A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

This invention has for purpose to provide a photosensor that is small in size and can obtain high-contrast image data and to provide a semiconductor device including the photosensor. In the photosensor including a light-receiving element, a transistor serving as a switching element, and a charge retention node electrically connected to the light-receiving element through the transistor, the reduction in charge held in the charge retention node is suppressed by extending the fall time of the input waveform of a driving pulse supplied to the transistor to turn off the transistor.

A display device includes a plurality of pixels, wherein a first pixel of the plurality of pixels includes: a scan line extending in a first direction; a data line extending in a second direction intersecting the first direction; a switching thin film transistor (TFT) connected to the scan line and the data line; a driving TFT connected to the switching TFT and comprising a driving gate electrode; a storage capacitor comprising the driving gate electrode as a first electrode and a second electrode arranged above the first electrode and overlapping the first electrode; a horizontal driving voltage line extending from the second electrode in the first direction; and a vertical driving voltage line extending from the second electrode in the second direction, wherein the horizontal driving voltage line, the vertical driving voltage line, and the data line are arranged over a same layer.

A solid-state imaging device includes light receiving sections which are arranged in an image area on a semiconductor substrate at the same pitch and which light exiting from an imaging optical system enters, condensing lenses respectively arranged above the light receiving sections, and light shielding sections each of which is provided at one end of each of the light receiving sections. The condensing lenses are arranged in a peripheral portion in a first direction in the image area at a first pitch, and arranged in a peripheral portion in a second direction opposite the first direction at a second pitch which is smaller than the first pitch.

A solid-state imaging device includes light receiving sections which are arranged in an image area on a semiconductor substrate at the same pitch and which light exiting from an imaging optical system enters, condensing lenses respectively arranged above the light receiving sections, and light shielding sections each of which is provided at one end of each of the light receiving sections. The condensing lenses are arranged in a peripheral portion in a first direction in the image area at a first pitch, and arranged in a peripheral portion in a second direction opposite the first direction at a second pitch which is smaller than the first pitch.

Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.

Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.

An integrated optical block that is highly portable and compact, designed to measure cells and particles.

A device that may include a pixel, an output conductor and a charge accelerator; wherein during a readout phase of the pixel, the pixel is configured to attempt to charge the output conductor to a pixel reset voltage and the charge accelerator is configured to perform a sampling operation and a charge operation; wherein during the sampling operation the charge accelerator is configured to sample a change in an output conductor voltage; wherein during the charge operation the charge accelerator is configured to output a charge accelerator output signal that is responsive to the change of the output conductor voltage, wherein once provided, the charge accelerator output signal accelerates a charging of the output conductor to a target voltage that is proximate to the pixel reset voltage; wherein the sampling operation and the charge operation do not overlap.