A system and method includes a power control circuit for controlling first power from a power supply provided to a first circuit includes a first stage and a second stage. The first stage includes a low power energy detector and a first power switch. The low power energy detector is configured to provide second power via the first switch in response to energy. The second stage includes a signal detector configured to detect a characteristic of a signal associated with the energy in response to the second power. The signal detector is configured have the first power provided to the first circuit in response to the characteristic being detected.

A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, and a charge storage film. The stacked body is provided on the substrate. The stacked body includes a plurality of first insulating films and a plurality of electrode films alternately stacked one layer by one layer. The semiconductor pillar is provided inside the stacked body and extends in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor pillar and each of the electrode films. The plurality of first insulating films include a first portion surrounding the semiconductor pillar and a second portion provided between the first portion and the semiconductor pillar, the second portion having a dielectric constant higher than a dielectric constant of the first portion.

Unwanted erosion of dielectric materials around a backside contact trench can be avoided or minimized employing an aluminum oxide liner. An aluminum oxide liner can be formed inside an insulating material layer in a backside contact trench to prevent collateral etching of the insulating material at an upper portion of the backside contact trench during an anisotropic etch that forms an insulating spacer. Alternatively, an aluminum oxide layer can be employed as a backside blocking dielectric layer. An upper portion of the aluminum oxide layer can be converted into an aluminum compound layer including aluminum and a non-metallic element other than oxygen at an upper portion of the trench, and can be employed as a protective layer during formation of a backside contact structure.

Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.

In a plasma processing apparatus according to an exemplary embodiment, a gas supply system supplies a gas into a processing container. A plasma source excites the gas supplied by the gas supply system. A support structure holds a processing target within the processing container. The support structure is configured to rotatably and tiltably support the processing target. The plasma processing apparatus further includes a bias power supply unit that applies a pulse-modulated DC voltage, as a bias voltage for ion attraction, to the support structure.

Technology is described for generating a valid token control signal from control signals from a row driver. In one example, a matrix type integrated circuit includes a row driver module and a 2D array of cell elements. The row driver module includes a voting logic module and at least two row drivers configured to generate control signals on at least two communal lines for cell elements of a row of the 2D array. Each row driver is configured to generate control signals on at least three control lines where at least two control lines are the communal lines and coupled to a corresponding communal line of another row driver. The voting logic module is coupled to the at least three control lines of one of the row drivers and configured to generate an output based on the control signals on the at least three control lines.

A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.