A semiconductor integrated circuit device may include a semiconductor chip, a power line region and a reservoir capacitor. The semiconductor chip may include a cell region and a peripheral circuit region. The power line region may be arranged on an edge portion of the peripheral circuit region. The reservoir capacitor may be formed on the power line region.

A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.

An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

According to one embodiment, a first semiconductor body extends in a stacking direction of a stacked body through a first stacked unit and contacts a foundation layer. A plurality of contact vias extend in the stacking direction through an insulating layer and contact a plurality of terrace portions. A second semiconductor body extends in the stacking direction through a second stacked unit. An insulating film is provided between the foundation layer and a lower end portion of the second semiconductor body.

A semiconductor memory device according to one embodiment includes a substrate, a stacked body provided on a first-direction side of the substrate, a semiconductor member extending in the first direction, and a charge storage film provided between the stacked body and the semiconductor member. The stacked body includes first insulating films and electrode films stacked alternately along the first direction. A recess is made in a surface of the stacked body facing the semiconductor member every one of the electrode films.

An etching method of etching a first region including a multilayered film, in which silicon oxide films and silicon nitride films are alternately stacked, and a second region including a single-layered silicon oxide film is provided. The etching method includes a first plasma process of generating plasma of a first processing gas containing a fluorocarbon gas and an oxygen gas within a processing vessel of a plasma processing apparatus; and a second plasma process of generating plasma of a second processing gas containing a hydrogen gas, nitrogen trifluoride gas, a hydrogen bromide gas and a carbon-containing gas within the processing vessel. A temperature of an electrostatic chuck is set to a first temperature in the first plasma process, and the temperature of the electrostatic chuck is set to a second temperature lower than the first temperature in the second plasma process.

An antifuse structure including an opening through a dielectric material to a contact surface and an antifuse material layer present within the opening. The antifuse material layer may be a phase change material alloy of tantalum and nitrogen, wherein at least a base surface of the antifuse material layer is present on the contact surface and sidewall surfaces of the antifuse material layer are present on sidewalls of the opening through the dielectric material. An airgap or solid material core may be in the opening atop the base surface of the phase change material alloy. An electrically conductive material may be in direct contact with at least the antifuse material layer.

A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.

The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.

An object is to provide an MRAM dry etching residue removal composition capable of removing dry etching residues while suppressing damage to a substrate containing a specific metal in a step of producing an MRAM, a method of producing a magnetoresistive random access memory using the same, and a cobalt removal composition having excellent cobalt removability.

The MRAM dry etching residue removal composition of the present invention contains a strong oxidizing agent and water. In addition, the cobalt removal composition of the present invention contains orthoperiodic acid and water.