A vertical nitride semiconductor device includes an n-type aluminum nitride single-crystal substrate having an Si content of 3×10.sup.17 to 1×10.sup.20 cm.sup.−3 and a dislocation density of 10.sup.6 cm.sup.−2 or less. An ohmic electrode layer is formed on an N-polarity side of the n-type aluminum nitride single-crystal substrate.

This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.

A method includes receiving a precursor having a substrate and first and second pluralities of gate structures, the first pluralities having a greater pitch than the second pluralities. The method further includes depositing a dielectric layer covering the substrate and the first and second pluralities; and performing an etching process to the dielectric layer. The etching process removes a first portion of the dielectric layer over the substrate, while a second portion of the dielectric layer remains over sidewalls of the first and second pluralities. The second portion of the dielectric layer is thicker over the sidewalls of the second plurality than over the sidewalls of the first plurality. The method further includes etching the substrate to form third and fourth pluralities of recesses adjacent the first and second pluralities, respectively; and epitaxially growing fifth and sixth pluralities of semiconductor features in the third and fourth pluralities, respectively.

A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of side-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of tip-to-side shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

An array substrate, a method for manufacturing the same and a display device are provided. The method includes: providing a base substrate; forming a conductive material thin film on the base substrate; forming a first photoresist layer on a side of the conductive material thin film distal to the base substrate; etching the conductive material thin film by using the first photoresist layer as a mask to obtain a first etched pattern; removing third covering portions of the first photoresist layer to obtain a second photoresist layer; and etching the first etched pattern by using the second photoresist layer as a mask to obtain a gate electrode and a signal line.

A semiconductor module including a semiconductor element, a controller, a cooler, and a temperature sensor are included. The controller is connected to the semiconductor module and controls switching operation of the semiconductor element. The temperature sensor measures a coolant temperature, which is a temperature of the coolant. The controller controls turn-off speed of the semiconductor element based on the coolant temperature. The controller increases the turn-off speed as the coolant temperature rises.

A semiconductor package includes a semiconductor device having a through silicon via, a lower redistribution structure on the semiconductor device, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the through silicon via, a package connection terminal on the lower redistribution structure and electrically connected to the lower redistribution pattern, an upper redistribution structure on the semiconductor device and including an upper redistribution insulating layer and an upper redistribution pattern electrically connected to the through silicon via, a conductive via in contact with the upper redistribution pattern and on the upper redistribution insulating layer, a connection pad on the conductive via, and a passive element pattern on the upper redistribution structure and electrically connected to the conductive via.

One object is to provide a semiconductor device with a structure which enables reduction in parasitic capacitance sufficiently between wirings. In a bottom-gate type thin film transistor including a stacked layer of a first layer which is a metal thin film oxidized partly or entirely and an oxide semiconductor layer, the following oxide insulating layers are formed together: an oxide insulating layer serving as a channel protective layer which is over and in contact with a part of the oxide semiconductor layer overlapping with a gate electrode layer; and an oxide insulating layer which covers a peripheral portion and a side surface of the stacked oxide semiconductor layer.

A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

A thyristor device that can include a disc-shaped device comprising a semiconductor material forming alternating p-n-p-n type layers. The device can include a gate area extending from an external gate lead contact point to a plurality of thyristor units connected in parallel. Each thyristor unit can include at least one exposed pB layer portion to form at least one plural point to which gate current can be directed. Further, an insulator layer can be formed over the gate area to insulate at least a portion of the gate electrode from the pB layer so that displacement current can be directed to short dots and then to the plural points. Current entering each thyristor unit can generate a turned-on area at each thyristor unit that spreads throughout the thyristor device.