An array substrate, a manufacturing method thereof and an organic light emitting diode display device are provided. The manufacturing method of the array substrate includes forming a first thin film transistor including a first semiconductor pattern, including forming a first electrode pattern including a first source electrode and a first drain electrode and a second electrode pattern including a first auxiliary source electrode and a first auxiliary drain electrode respectively through two patterning processes; forming a second thin film transistor including forming a second source electrode and a second drain electrode through one patterning process. The second electrode pattern, the second source electrode and the second drain electrode are formed in the same patterning process, the first electrode pattern is connected with the first semiconductor pattern.

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The first insulating layer is in contact with part of the top surface of the semiconductor layer, the conductive layer is positioned over the first insulating layer, and the second insulating layer is positioned over the semiconductor layer. The semiconductor layer contains a metal oxide and includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer. The second region is in contact with the second insulating layer. The second insulating layer contains oxygen and a first element. The first element is one or more of phosphorus, boron, magnesium, aluminum, and silicon.

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition. A remaining portion of the at least partially relaxed semiconductor material is removed to provide a plurality of fin structure of the first strained semiconductor material.

A method of forming a semiconductor structure includes forming a seed layer over a top surface of a substrate and a protect layer over a top surface of the seed layer. The method also includes forming a magnetic film on a top surface of the protect layer and a top surface of the substrate in at least one opening formed in the seed layer and the protect layer. The method further includes forming at least one patterned magnetic feature on the top surface of the substrate by electro-etching the magnetic film, wherein the seed layer provides a self-stop for the electro-etching of the magnetic film.

A semiconductor substrate is a provided and an insulating layer is formed thereon. A cavity structure is formed above the insulating layer, including a lateral growth channel and a fin seed structure arranged in the lateral growth channel. The fin seed structure provides a seed surface for growing a fin structure. One or more first semiconductor structures of a first semiconductor material and one or more second semiconductor structures of a second, different, semiconductor material are grown sequentially in the growth channel from the seed surface in an alternating way. The first semiconductor structures provide a seed surface for the second semiconductor structures and the second semiconductor structures provide a seed surface for the first semiconductor structures. The second semiconductor structures are selectively etched, thereby forming the fin structure comprising a plurality of parallel fins of the first semiconductor structures. Corresponding semiconductor structures are also included.

After forming a sacrificial gate structure straddling a stacking of a semiconductor mandrel structure and a dielectric mandrel cap and spacers present on sidewalls of the stack, portions of the spacers located on opposite sides of the sacrificial gate structure are removed. Epitaxial source/drain regions are formed on exposed sidewalls of portions of the semiconductor mandrel structure located on opposite sides of the sacrificial gate structure. The sacrificial gate structure is removed to provide a gate cavity. Next, portions of the spacers exposed by the gate cavity are removed to expose sidewalls of a portion of the semiconductor mandrel structure. III-V compound semiconductor channel portions are then formed on exposed sidewalls of the semiconductor mandrel structure. Portions of the semiconductor mandrel structure and the dielectric mandrel cap exposed by the gate cavity are subsequently removed from the structure, leaving only the III-V compound semiconductor channel portions.

The present invention proposes an array substrate and a method for fabricating the same. According to the array substrate and the method of fabricating the array substrate in the present invention, the IGZO pattern and the first electrode strip, the first channel, and the second metallic layer in the corresponding section form the first transistor of the CMOS inverter, and the OSC pattern and the second electrode strip, the second channel, and the second metallic layer in the corresponding section form the second transistor of the CMOS inverter. In this way, the CMOS inverter or the CMOS ring oscillator is fabricated based on IGZO and OSC.

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.