An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

A memory cell can include a phase change material layer and a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side. A carbon nitride layer can be on the bit line side surface of the first electrode layer. In some examples, a nonconductive separator material can have a word line end and a bit line end, and can have a portion contacting the phase change material layer. The bit line end surface of the nonconductive separator material can be at least partially free of contact with the carbon nitride layer.

The purpose of the present invention is to realize the display device having thin film transistors of the oxide semiconductor of stable characteristics. An example of the concrete structure is that: A display device having a substrate including a display area, plural pixels formed in the display area, the pixel includes a first thin film transistor having an oxide semiconductor film, a first insulating film made of a first silicon oxide on a first side of the oxide semiconductor film, a second insulating film made of a second silicon oxide on a second side of the oxide semiconductor film, wherein oxygen desorption amount per unit area from the first insulating film is larger than that from the second insulating film, when measured by TDS (Thermal Desorption Spectrometry) provided M/z=32 and a measuring range in temperature is from 100 centigrade to 500 centigrade.

A semiconductor device is fabricated by a method including the following steps: a first step of forming a semiconductor film containing a metal oxide over an insulating layer; a second step of forming a conductive film over the semiconductor film; a third step of forming a first resist mask over the conductive film and etching the conductive film to form a first conductive layer and to expose a top surface of the semiconductor film that is not covered with the first conductive layer; and a fourth step of forming a second resist mask that covers a top surface and a side surface of the first conductive layer and part of the top surface of the semiconductor film and etching the semiconductor film to form a semiconductor layer and to expose a top surface of the insulating layer that is not covered with the semiconductor layer.

A method and a system for developing semiconductor device fabrication processes are provided. The developments of vertical and lateral semiconductor device fabrication processes can be integrated in the system. First, according to a target semiconductor device and a specification thereof, an initial target model and a general database are captured. The initial target model and the general database are compared to obtain a corresponding relationship. According to the corresponding relationship, multiple fixed fabrication parameters of the general database are applied to the initial target model, such that at least one adjustable parameter is defined. Thereafter, the parameter is set according to a setting instruction received through a user interface to produce a target model to be simulated. A simulation test is performed with the target model, and the adjustable parameter is modified until the simulation result of the target model satisfies a standard result.

An apparatus includes a first drain/source region and a second drain/source region over a substrate, and a first gate adjacent to the first drain/source region, a second gate adjacent to the second drain/source region and a third gate between the first gate and the second gate, wherein the first drain/source region, the second drain/source region, the first gate, the second gate and the third gate form two back-to-back connected transistors.

The present application provides a process method for improving reliability of a metal gate high-voltage device. Stacks layers formed over the gate oxide layer and spaced apart from each other. An SiCN layer is deposited to cover tops and sidewalls of the stack layers, and cover bottoms of slots between the stack layers. An HARP layer is deposited to covert the SiCN layer. The HARP layer over the stack layers and the slot regions is covered with a photoresist. Photolithography and etching are sequentially performed to open the HARP layer over the stack layers. The photoresist in the slot regions is reserved. The HARP layer over the stack layers outside the slot regions is removed. The operations are repeated for many times until the slot regions are filled with the HARP layer.

A TFT includes an oxide semiconductor layer including a conductive region electrically connected to a source electrode, a conductive region electrically connected to a drain electrode, a channel region being an oxide semiconductor region that overlaps a gate electrode, and at least one resistive region being an oxide semiconductor region provided between the channel region and a conductive region adjacent to the channel region.

A thin-film transistor substrate includes an insulating substrate, a first insulating layer, a first thin-film transistor including a first oxide semiconductor film, a second insulating layer located upper than the first insulating layer, and a second thin-film transistor including a second oxide semiconductor film different in composition from the first oxide semiconductor film. At least a part of the first oxide semiconductor film is provided above and in contact with the first insulating layer. The first insulating layer is the uppermost insulating layer among insulating layers located lower than and in contact with the first oxide semiconductor film. At least a part of the second oxide semiconductor film is provided above and in contact with the second insulating layer. The second insulating layer is the uppermost insulating layer among insulating layers located lower than and in contact with the second oxide semiconductor film.

Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.