A drive backplane and a display panel are provided, the drive backplane includes: a substrate; and an oxide thin film transistor arranged on the substrate, wherein the oxide thin film transistor includes: an oxide active layer; a first gate structure disposed on a side of the oxide active layer away from the substrate; and a second gate structure disposed between the oxide active layer and the substrate; wherein at least one of the first gate structure and the second gate structure comprises a plurality of gate electrodes spaced apart along a direction in which the oxide active layer extends.

Disclosed is a display apparatus including a first thin film transistor (TFT) and a second thin film transistor having a bottom gate structure and including an oxide semiconductor layer. The first TFT may be used as a switching device and the second TFT may be used as a driving device, and these TFTs have different operation properties from each other. One or more embodiments of the present disclosure provides a method of arranging a plurality of TFTs having different properties in a display apparatus. This not only provides a display apparatus with TFTs integrated at a high density but also an efficient way of driving the display apparatus.

A display apparatus includes a first TFT in a display area including a first semiconductor pattern including a polysilicon, a first gate electrode overlapping with the first semiconductor pattern under conditions that a first gate insulating layer is interposed, and first source and drain electrodes connected to the first semiconductor pattern, a second TFT in the display area including a second semiconductor pattern including a first oxide semiconductor, a second gate electrode overlapping with the second semiconductor pattern under conditions that second and third gate insulating layers are interposed, second source and drain electrodes connected to the second semiconductor pattern, and a third TFT in a non-display area including a third semiconductor pattern including a second oxide semiconductor, a third gate electrode overlapping with the third semiconductor pattern under conditions that the third gate insulating layer is interposed, and third source and drain electrodes connected to the third semiconductor pattern.

A display device includes a buffer layer disposed on a substrate and comprising a first buffer film, and a second buffer film, wherein the first buffer film and the second buffer film are sequentially stacked in a thickness direction of the display device; a semiconductor pattern disposed on the buffer layer; a gate insulating layer disposed on the semiconductor pattern; and a gate electrode disposed on the gate insulating layer, wherein the first buffer film and the second buffer film comprise a same material, and a density of the first buffer film is greater than a density of the second buffer film.

A number of monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a monolithic multi-throw diode switch have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm.

A number of monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a monolithic multi-throw diode switch have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm.

A thin film transistor panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate and including a first semiconductor layer including a low temperature polysilicon and a first control electrode overlapping the first semiconductor layer; a second transistor disposed on the substrate and including a second semiconductor layer including an oxide semiconductor and a second control electrode overlapping the second semiconductor layer; a first gate insulation layer disposed between the first semiconductor layer and the first control electrode of the first transistor and including a first insulation layer and a second insulation layer; and a second gate insulation layer disposed between the second semiconductor layer and the second control electrode of the second transistor and including the second insulation layer, wherein the density of the first insulation layer may be higher than the density of the second insulation layer, the first semiconductor layer of the first transistor may be in contact with the first insulation layer, and the second semiconductor layer of the second transistor may be in contact with the second insulation layer.

An active matrix substrate includes a thin film transistor that includes a gate electrode, a first inorganic insulating film that covers the gate electrode, a second inorganic insulating film that is disposed on the first inorganic insulating film and that has an opening overlapping the gate electrode, a source electrode and a drain electrode disposed on the second inorganic insulating film, and a semiconductor layer that overlaps the gate electrode in an opening of the first inorganic insulating film and that covers the source electrode and the drain electrode. Regarding a surface of the first inorganic insulating film in a first region overlapping the opening of the first inorganic insulating film and a surface in a second region other than the first region, the surfaces being arranged nearer to the second inorganic insulating film, the surface in the first region is lower than the surface in the second region.

A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

A semiconductor structure for RF applications comprises: a first μTP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.