A layered structure used for detecting incident light includes a substrate having a surface with a high Miller index crystal orientation and a superlattice structure formed over the substrate at the surface. The superlattice structure is aligned to the high Miller index crystal orientation and exhibits a red-shifted long wave infrared response range based on the crystal orientation as compared to a superlattice structure formed over a substrate at a surface with a (100) crystal orientation.

Disclosed is a solar cell including a first electrode, a second electrode, and a first conversion layer disposed therebetween. The first electrode is closer to a light incident side than the second electrode. The first conversion layer is a composition-gradient perovskite. A part of the first conversion layer adjacent to the first electrode has an energy gap less than that of a part of the first conversion layer adjacent to the second electrode.

A scanning electron microscope incorporates a multi-pixel solid-state electron detector. The multi-pixel solid-state detector may detect back-scattered and/or secondary electrons. The multi-pixel solid-state detector may incorporate analog-to-digital converters and other circuits. The multi-pixel solid state detector may be capable of approximately determining the energy of incident electrons and/or may contain circuits for processing or analyzing the electron signals. The multi-pixel solid state detector is suitable for high-speed operation such as at a speed of about 100 MHz or higher. The scanning electron microscope may be used for reviewing, inspecting or measuring a sample such as unpatterned semiconductor wafer, a patterned semiconductor wafer, a reticle or a photomask. A method of reviewing or inspecting a sample is also described.

A scanning electron microscope incorporates a multi-pixel solid-state electron detector. The multi-pixel solid-state detector may detect back-scattered and/or secondary electrons. The multi-pixel solid-state detector may incorporate analog-to-digital converters and other circuits. The multi-pixel solid state detector may be capable of approximately determining the energy of incident electrons and/or may contain circuits for processing or analyzing the electron signals. The multi-pixel solid state detector is suitable for high-speed operation such as at a speed of about 100 MHz or higher. The scanning electron microscope may be used for reviewing, inspecting or measuring a sample such as unpatterned semiconductor wafer, a patterned semiconductor wafer, a reticle or a photomask. A method of reviewing or inspecting a sample is also described.

Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The semiconductor can also include an absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1×10.sup.16 cm.sup.−3 at room temperature. The semiconductor can also include a second doped III-V layer over the absorber layer.

A photodetector includes an array of pixels, each pixel comprising a defined doped region defined in a doped semiconductor layer. The defined doped region is defined by selected regions of ion implants to provide resistive isolation between each defined doped region. A capacitor is formed by the defined doped region and a metal layer disposed above the doped semiconductor layer. A contact metal line is disposed above the doped semiconductor layer. The capacitor metal and contact metal lines are electrically coupled together and are in electrical communication with the output of the photodetector array.

A photodetector includes an array of pixels, each pixel comprising a defined doped region defined in a doped semiconductor layer. The defined doped region is defined by selected regions of ion implants to provide resistive isolation between each defined doped region. A capacitor is formed by the defined doped region and a metal layer disposed above the doped semiconductor layer. A contact metal line is disposed above the doped semiconductor layer. The capacitor metal and contact metal lines are electrically coupled together and are in electrical communication with the output of the photodetector array.

A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

The inventive concepts relate to image sensors. The image sensor includes a substrate including a floating diffusion region and a pixel circuit, an interlayer insulating layer on the substrate, a contact node and a first electrode on the interlayer insulating layer, a dielectric layer on a top surface of the first electrode, a channel semiconductor pattern on the dielectric layer and connected to the contact node, and a photoelectric conversion layer on the channel semiconductor pattern. The channel semiconductor pattern includes a semiconductor material having an electron mobility that is higher than an electron mobility of the photoelectric conversion layer.

A transistor includes (i) a first wire including a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature and (ii) a second wire including a superconducting component configured to operate in a superconducting state while: a temperature of the superconducting component is below a superconducting threshold temperature and a first input current supplied to the superconducting component is below a current threshold. The semiconducting component is located adjacent to the superconducting component. In response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first input current exceeds the lowered current threshold.