A stacked multi-junction solar cell with a metallization comprising a multilayer system, wherein the multi-junction solar cell has a germanium substrate forming a bottom side of the multi-junction solar cell, a germanium subcell, and at least two III-V subcells, the multilayer system of the metallization has a first layer, comprising gold and germanium, a second layer comprising titanium, a third layer, comprising palladium or nickel or platinum, with a layer thickness, and at least one metallic fourth layer, and the multilayer system of the metallization covers at least one first and second surface section and is integrally connected to the first and second surface section, wherein the first surface section is formed by the dielectric insulation layer and the second surface section is formed by the germanium substrate or by a III-V layer.

A substrate current suppression circuit includes: a fixed voltage line that supplies a fixed voltage to the collectors of the third and fourth transistors. The fixed voltage is a voltage higher than the base voltage of the third and fourth transistors when the first polarity is p type, and is a voltage lower than the base voltage when the first polarity is n type.

Various embodiments set forth a light-emitting device, comprising a single die formed from a portion of a semiconductor substrate of a first conductivity type, a first vertical cavity surface-emitting laser (VCSEL) that is formed from a set of material layers disposed on a surface of the portion of the semiconductor substrate. and a first photodiode that is formed at the surface of the portion of the semiconductor substrate.

Present invention discloses a microfluidic energy harvester for converting solar energy into electrical energy. A preferred embodiment of the present microfluidic energy harvester includes a substrate having an embedded central microchannel, electrolyte configured to reside and/or flow in said central microchannel and electrode assembly having one or more pair of electrodes arranged in a series and integrated with said central microchannel from sides ensuring direct contact between said pair for electrodes with said electrolyte while it reside and/or flow in said central microchannel for ensuing electrochemical photovoltaic effect to convert the solar energy into the electrical energy under direct solar illumination by working under regenerative conditions. The microfluidic energy harvester is capable of producing high density power from three different resources, (a) the solar irradiation produces a photovoltaic potential difference between the metal/metal-oxide electrodes, (b) SPR of the metal nanoparticles suspended in the electrolyte amplifies the photovoltaic potential difference under solar irradiation, and (c) the flow of the nanoparticle laden electrolyte produces a streaming potential between the electrodes by converting the mechanical energy into the electrical one near the electrodes. The transparency of the polymer and adequate absorptivity of the metal/metal-oxide electrodes ensured facile absorption of solar irradiation in the microfluidic energy harvester. The flexibility of the MEH can be tuned by adjusting the cross-linking of the PDMS matrix. The multiplicity of the microchannels and electrodes are expected to increase the total amount of energy harvested.

A solar cell (1) includes a semiconductor substrate (10) having a light-receiving surface (10a) and a back surface (10b); an n-type semiconductor layer (13n) and a p-type semiconductor layer (12p) provided on the back surface (10b) of the semiconductor substrate (10), the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p) extending in a first direction and being adjacent to each other in a second direction intersecting with the first direction; and a ground layer (14) provided on the n-type semiconductor layer (13n) and the p-type semiconductor layer (12p). The ground layer (14) includes an n-side ground layer (14n) and a p-side ground layer (14p) separated from each other by a first separating groove (17) having a first separating portion (17a) and a second separating portion (17b) as well as a first bridge portion (18) separating the first separating portion (17a) and the second separating portion (17b). The first bridge portion (18) separates the first separating portion (17a) and the second separating portion (17b) at at least one of a border on the n-side ground layer (14n) or a border on the p-side ground layer (14p) in the first direction.

A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate.

Refractive optical element designs are provided for high geometric optical efficiency over a wide range of incident angles. To minimize Fresnel reflection losses, the refractive optical element designs employ multiple encapsulant materials, differing in refractive index. Concentrator photovoltaic subassemblies are formed by embedding a high efficiency photovoltaic device within the refractive optical element, along with appropriate electrical contacts and heat sinks. Increased solar electric power output is obtained by employing a single-junction III-V material structure with light-trapping structures.

Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.

A silicon solar cell with high photoelectric conversion efficiency is disclosed. A solar cell for converting light incident from an outside into electricity according to the present invention includes a substrate, a lower electrode, a ferroelectric layer, an auxiliary electrode, a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an upper electrode. The lower electrode is formed on the substrate. The ferroelectric layer is formed on the substrate and outside the lower electrode. The auxiliary electrode is formed on the ferroelectric layer. The first conductivity-type semiconductor layer is formed on the lower electrode and the auxiliary electrode. The second conductivity-type semiconductor layer is formed on the first conductivity-type semiconductor layer, and is composed of a semiconductor of a second conductivity type opposite to a first conductivity type. The upper electrode is made of transparent conductive material, and is formed on the second conductivity-type semiconductor layer.