This application provides semiconductor structures and methods of manufacturing the same. A semiconductor structure includes: an N-type semiconductor layer, a light emitting layer, and a P-type ion doped layer that are disposed from bottom to up, wherein the P-type ion doped layer comprises an activated region and non-activated regions located on two sides of the activated region, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated region are passivated. The layout of the activated region and the non-activated regions makes an LED include: a high-efficiency light emitting region and light emitting obstacle regions located on two sides of the high-efficiency light emitting region.

A substrate includes a base substrate, at least two bonding pads are arranged on the base substrate, the base substrate and an electronic element are bonded to each other through the at least two bonding pads, at least two pins are arranged on the electronic element, a protective layer is arranged at a side of the bonding pads away from the base substrate, and an opening region is arranged in the protective layer at each bonding pad, to expose partial surface of the bonding pad. A bonding combination layer made of a low-melting-point alloy material is arranged in the opening region, and the low-melting-point alloy material is capable of being melted at a first predetermined temperature, to enable the bonding pads and the pins to be bonded to each other.

A display apparatus includes a substrate including a component area and a main display area, the component area including sub display areas and transmission areas, main pixel electrodes disposed in the main display area and spaced apart from each other, sub pixel electrodes disposed in the sub display areas and spaced apart from each other, a pixel definition layer covering an edge of each of the main pixel electrodes and an edge of each of the sub pixel electrodes and including transmission holes in areas corresponding to the transmission areas, main spacers disposed on the pixel definition layer in the main display area, and sub spacers disposed on the pixel definition layer in the component area, wherein a number of the sub spacers per unit area is equal to a number of the main spacers per unit area in a plan view.

A micro-light emitting diode (LED) display panel and a method of forming the display panel, the micro-LED display panel having a monolithically grown micro-structure including a first color micro-LED that is a first color nanowire LED, and a second color micro-LED that is a second color nanowire LED.

Embodiments of the present disclosure relate to a transfer head assembly and an LED transfer apparatus, and more particularly, to a transfer head assembly and an LED transfer apparatus in which a plurality of pickup units picks up LEDs, which are adhered to the upper surfaces of the LEDs, and transfers the LEDs to a display substrate. According to the embodiments of the present disclosure, a large number of LEDs located on a wafer substrate or a carrier substrate can be transferred in bulk to a display substrate. Thus, it is possible to rapidly perform the transfer process of the LEDs.

An LED packaging device includes a frame including a bottom wall having a bottom surface and a surrounding wall extending upwardly from the bottom wall, at least one LED chip, a plurality of spaced-apart reflectors and a packaging body. The bottom and surrounding walls cooperatively define a mounting space. The surrounding wall has an internal side surface facing the mounting space and a top surface facing away from the bottom surface. The LED chip is disposed on the bottom surface and is received in the mounting space. Each of the reflectors is disposed on a peripheral region of the bottom surface. The packaging body covers the LED chip and the reflectors, such that the LED chip is sealed inside the mounting space.

In some embodiments, a semiconductor structure comprises a semiconductor layer, a metal layer, and a contact layer adjacent to the metal layer, and between the semiconductor layer and the metal layer. The contact layer can comprise one or more piezoelectric materials comprising spontaneous piezoelectric polarization that depends on material composition and/or strain, and a region comprising a gradient in materials composition and/or strain adjacent to the metal layer. In some embodiments, a light emitting diode (LED) device comprises an n-doped short period superlattice (SPSL) layer, an intrinsically doped AlN/GaN SPSL layer adjacent to the n-doped SPSL layer, a metal layer, and an ohmic-chirp layer between the metal layer and the intrinsically doped AlN/GaN SPSL layer.

A method for forming a common electrode is provided, including: a) providing a support substrate on which rest optoelectronic devices separated by trenches; b) forming a dielectric layer on front faces, flanks, and a bottom of the trenches, of a thickness E1 and a thickness E2, which is less than the thickness E1, at, respectively, the front faces and the flanks; c) etching a thickness E3 of the dielectric layer, so as to uncover the flanks at a first section of the trenches; d) forming a metal layer filling the trenches and covering the front faces; and e) performing a mechanochemical polishing of the metal layer, the polishing stopping on a portion of the dielectric layer, the metal layer remaining in the trenches forming the common electrode.

A wafer includes a buried substrate; a layer of silicon (100) disposed on the buried substrate and forming multiple U-shaped grooves, wherein each U-shaped groove comprises a bottom portion and silicon sidewalls (111) at an angle to the buried substrate; a buffer layer disposed within the multiple U-shaped grooves; and multiple gallium nitride (GaN)-based structures having vertical sidewalls disposed within and protruding above the multiple U-shaped grooves, the multiple GaN-based structures each including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111).

A method of making a surface-mountable pixel engine package comprises providing an array of spaced-apart conductive pillars and an insulating mold compound laterally disposed between the conductive pillars on a substrate together defining a planarized surface. Pixel engines comprising connection posts are printed to the conductive pillars so that each of the connection posts is in electrical contact with one of the conductive pillars. The pixel engines are tested to determine known-good pixel engines. An optically clear mold compound is provided over the planarized surface and tested pixel engines. Optically clear mold compound is adhered to a tape and the substrate is removed. The optically clear mold compound, the insulating mold compound, the conductive pillars, the optically clear mold compound, and the tested pixel engines are singulated to provide pixel packages that comprise the pixel engines and the known-good pixel engines are transferred to a reel or tray.