A leakage current interruption device comprises: the leakage current interruption device in which it is coupled electrically between the power switch and the load: the first and second input stages coupled with a side of the power source; the first and second output stages coupled with a side of the load; the first and second switching members for turning on and off respectively the electrical connection between the first and second input stages and the first and second output stages; a switching driving member in which it is coupled between the first and second input stages and generates and outputs a switching driving signal to turn on or off the first and second switching members according to the on or off signals of the power switch.

A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Systems, methods, and computer-readable media are disclosed for high impedance detection in electric distribution systems. An example method may include calculating, by a processor, a relative randomness of a signal, wherein the relative randomness is a derivative of a first scale wavelet transform divided by an energy of the signal. The example method may also include calculating, by the processor, one or more scales of a wavelet transform of the signal. The example method may also include calculating, by the processor, one or more energy ratios between energy of the wavelet transform in the one or more scales. The example method may also include calculating, by the processor, a zero-crossing phase difference between a third harmonic and a fundamental component of the signal. The example method may also include determining, by the processor, that a high impedance fault occurs based on at least one of: the relative randomness, a comparison between the one or more scales of the wavelet transform, and the zero-crossing phase difference.

In some examples, a device includes a memory configured to store a pre-warning threshold level for a parameter of a power switch. The device also includes a logic circuit configured to receive a signal from a controller and set the pre-warning threshold level in response to receiving the signal from the controller. The logic circuit is also configured to determine that a magnitude of the parameter of the power switch does not satisfy the pre-warning threshold level. The logic circuit is further configured to output an alert to the controller in response to determining that the magnitude of the parameter does not satisfy the pre-warning threshold level.

A power system includes multiple power units (PUs), each including a circuit breaker (CB), a local controller (LC) and an intelligent electronic device (IED). For any one of the PUs, the IED, when determining that the CB has mechanically failed, outputs a disconnect message via a network to the IED(s) of the remaining PU(s). For each of the remaining PU(s), based on the disconnect message, the IED thereof, when determining that the corresponding CB is a relevant CB, outputs a trip control signal that indicates to trip for receipt by the corresponding LC, so that the LC causes the CB to switch to an open state.

Methods for arc detection in a system including one or more photovoltaic generators, one or more photovoltaic power devices and a system power device and/or a load connectible to the photovoltaic generators and/or the photovoltaic power devices. The methods may measure voltage, current, and/or power delivered to the load or system power device, and the methods may measure voltage noise or current noise within the photovoltaic system. The methods may periodically, and/or in response to detecting noise, reduce an electrical parameter such as current or voltage in order to extinguish an arc. The methods may compare one or more measurements to one or more thresholds to detect arcing, and upon a comparison indicating that arcing is or was present, an alarm condition may be set.

An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer, and being coupled to the first voltage supply. The first diode is in the semiconductor wafer, and coupled between an IO pad and a first node. The second diode is in the semiconductor wafer, coupled to the first diode and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled between the first node and the second node, and further coupled to the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.

Methods for determining a line fault of a power system. The methods include obtaining sampled values of voltages and currents of phases of a power line in the power system, determining a phase compensation voltage of a first phase and an interphase compensation voltage of an interphase loop between a second phase and a third phase, and detecting the line fault in the first phase and/or the interphase loop by comparing the phase compensation voltage and the interphase compensation voltage.

An arc flash suppressor, system, and method are disclosed. The arc flash suppressor includes a main processor, a current sensor processor, a voltage sensor processor, a plasma ignition detector, and an arc flash extinguishing circuit. The current sensor processor is configured to detect a slew rate of an input current from a power source. The voltage sensor processor is configured to detect a slew rate of an input voltage from the power source. The main processor is configured to cause the arc flash extinguishing circuit to create a short circuit condition over the power source to extinguish an arc flash upon detection of a critical current slew rate, a critical voltage slew rate, and plasma ignition.

A surge protective device (SPD) assembly includes a base and an SPD module configured to be mounted on the base. The SPD module includes an SPD module PCB, an SPD module circuit, and a thermal disconnector mechanism. The SPD module circuit is at least partly embodied in the SPD module PCB and includes an overvoltage protection component mounted on the SPD module PCB. The thermal disconnector mechanism is mounted on the SPD module PCB in a ready configuration. The thermal disconnector mechanism is operative to transition from the ready configuration to an actuated configuration responsive to sufficient overheating of the overvoltage protection component. When the thermal disconnector mechanism is positioned in the ready configuration, the SPD circuit forms a first current path through the overvoltage protection component. When the thermal disconnector mechanism is positioned in the actuated configuration, the thermal disconnector mechanism forms an alternate second current path that bypasses the overvoltage protection component.