A capacitor circuit includes a first terminal, a first to a third transistor and a first capacitor. The first transistor includes a first terminal configured to be coupled to a first current source and the first terminal of the capacitor circuit, and a second terminal coupled to a reference voltage terminal. The second transistor includes a first terminal configured to be coupled to a second current source, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the first terminal of the second transistor and a control terminal of the first transistor. The third transistor includes a first terminal configured to be coupled to a third current source and the first terminal of the first transistor, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the control terminal of the second transistor. The first capacitor includes a first terminal coupled to the first terminal of the capacitor circuit, and a second terminal coupled to the control terminal of the first transistor.

An oscillator assembly includes a scribe seal, an oscillator circuit, and a calibration circuit. The oscillator circuit includes an output. The calibration circuit is coupled to the oscillator circuit. The calibration circuit includes a reference frequency terminal, a conductor coupled to the reference frequency terminal, and an oscillator input terminal. The conductor extends to an edge of the oscillator circuit assembly and penetrates the scribe seal. The oscillator input terminal is coupled to the output of the oscillator circuit.

An oscillator assembly includes a scribe seal, an oscillator circuit, and a calibration circuit. The oscillator circuit includes an output. The calibration circuit is coupled to the oscillator circuit. The calibration circuit includes a reference frequency terminal, a conductor coupled to the reference frequency terminal, and an oscillator input terminal. The conductor extends to an edge of the oscillator circuit assembly and penetrates the scribe seal. The oscillator input terminal is coupled to the output of the oscillator circuit.

An input circuit includes an input stage having an input node and a direct-current (DC) amplifier coupled to the input node. The input circuit also includes an alternating-current (AC) amplifier coupled to an output node of the DC amplifier. The input circuit also includes a capacitor coupled between the input node and the output node of the DC amplifier. The input circuit also includes a voltage divider coupled to the DC amplifier and the AC amplifier. The voltage divider includes first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, where the first resistor is larger than the second resistor.

An oscillator includes a substrate having a first substrate main surface and a substrate side surface, and a lid body bonded to the substrate and including a metal material, in which the substrate includes a substrate body having a first substrate body main surface corresponding to the first substrate main surface and a substrate body side surface corresponding to the substrate side surface, and provided with a cutout portion in the substrate body side surface, a side surface wiring provided along the cutout portion, a filling member provided in the cutout portion, and an insulating coating member provided on the first substrate body main surface.

A semiconductor device includes a main switching circuit implemented by a first semiconductor element and a second semiconductor element having a semiconductor region of a first conductivity type as a common region, including respectively a first well region of a second conductivity type and a second well region of a second conductivity type provided in an upper portion of the common region, the first semiconductor element being provided with a first source region of the first conductivity type in an upper portion of the first well region, the second semiconductor element being provided with a second source region of the first conductivity type in an upper portion of the second well region; and a drive circuit configured to independently apply a first drive signal and a second drive signal respectively to a control electrode of the first semiconductor element and a control electrode of the second semiconductor element.

A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.

One or more embodiments are directed to inter-integrated circuit (I2C) transmitters, receivers, and devices that utilize a stable reference voltage for driving a pre-driver of the transmitter and for driving a first input stage of the receiver. One embodiment is directed to a device A device that includes an inter-integrated circuit (I2C) transmitter and an I2C receiver. The I2C transmitter includes a driver coupled to an I2C data line, and a pre-driver coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver is configured to output a control signal to a control terminal of the driver. The I2C receiver includes a first stage coupled to the I2C data line, the variable first supply voltage, the second supply voltage, and the reference voltage.

A switching control circuit that controls on/off of a switching element is provided to efficiently disperse EMI noise due to high-speed switching, the switching control circuit includes a gate driver, a variable capacitance element connected to a gate of the switching element, and a capacitance changing circuit that randomly changes a capacitance of the variable capacitance element.

A half buffer circuit includes a current source coupled to a first node, a ground connection coupled to a second node, a feedback capacitor coupled between the first node and an output of the half buffer circuit, a transconductor element comprising a first input/output, a second input/output, and a transconductor element control input, and a switch network coupled between the first node and the second node. The first input/output is coupled to the output of the half buffer circuit. The second input/output is coupled to a ground connection. The switch network includes a first switch coupled between the first node and the second node, a second switch coupled between the first node and the transconductor element control input, and a third switch coupled between the second node and the transconductor element control input.