A frequency multiplier, a digital phase-locked loop circuit, and a frequency multiplication method, where the frequency multiplier includes a clock controller configured to: receive an output signal from a time-to-digital converter in the digital phase-locked loop circuit, and generate a control signal based on a duty cycle error of the output signal, a clock calibration circuit configured to: receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal, and a clock frequency multiplier configured to: receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter.

A frequency multiplier, a digital phase-locked loop circuit, and a frequency multiplication method, where the frequency multiplier includes a clock controller configured to: receive an output signal from a time-to-digital converter in the digital phase-locked loop circuit, and generate a control signal based on a duty cycle error of the output signal, a clock calibration circuit configured to: receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal, and a clock frequency multiplier configured to: receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter.

Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers. In one embodiment, the complementary frequency multiplier module includes a complementary pair of FETs controlled by an applied base oscillator signal. The complementary FETs are coupled to a common-gate FET amplifier and alternate becoming conductive in response to the base oscillator signal. The alternating switching of the complementary FETs in response to the opposing phases of the base oscillator signal cause the common-gate FET amplifier to output a higher frequency local oscillator (LO) signal. The LO signal is coupled to the LO input of a mixer or mixer core of a type suitable for use in conjunction with a frequency multiplier.

An apparatus for determining whether an output signal from an injection locked oscillator is synchronized with an injection signal coming from an input oscillator has a distorter and a level detector. The distorter uses the output signal from the injection locked oscillator to generate a distorter output signal which has a difference tone in a predetermined frequency band if the output signal from the injection locked oscillator is not synchronized with the injection signal. The level detector is designed to detect a level of the difference tone. The apparatus determines, on the basis of the level of the difference tone, whether the output signal from the injection locked oscillator is synchronized with the injection signal.

An apparatus for determining whether an output signal from an injection locked oscillator is synchronized with an injection signal coming from an input oscillator has a distorter and a level detector. The distorter uses the output signal from the injection locked oscillator to generate a distorter output signal which has a difference tone in a predetermined frequency band if the output signal from the injection locked oscillator is not synchronized with the injection signal. The level detector is designed to detect a level of the difference tone. The apparatus determines, on the basis of the level of the difference tone, whether the output signal from the injection locked oscillator is synchronized with the injection signal.

A frequency multiplier, a digital phase-locked loop circuit, and a frequency multiplication method, where the frequency multiplier includes a clock controller configured to: receive an output signal from a time-to-digital converter in the digital phase-locked loop circuit, and generate a control signal based on a duty cycle error of the output signal, a clock calibration circuit configured to: receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal, and a clock frequency multiplier configured to: receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter.

An apparatus for determining whether an output signal from an injection locked oscillator is synchronized with an injection signal coming from an input oscillator has a distorter and a level detector. The distorter uses the output signal from the injection locked oscillator to generate a distorter output signal which has a difference tone in a predetermined frequency band if the output signal from the injection locked oscillator is not synchronized with the injection signal. The level detector is designed to detect a level of the difference tone. The apparatus determines, on the basis of the level of the difference tone, whether the output signal from the injection locked oscillator is synchronized with the injection signal.

A carrier recovery system for a receiver of a phase-modulated signal N-PSK, the system including a first pre-conditioning circuit of the signal received (S(t)), with the pre-conditioned signal (SP(t)) having a component, non-modulated in phase, at the frequency N.sub.c where .sub.c is the carrier used for the modulation N-PSK, and a carrier regeneration circuit to regenerate two sinusoidal signals in quadrature at the frequency .sub.c, with these signals being phase locked with respect to said non-modulated component in phase of the pre-conditioned signal.

An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.

An apparatus for performing a frequency multiplication of an mm-wave wave signal is provided. The apparatus includes a first differential circuit that is capable of receiving a 0 phase component of an input signal and a 180 phase component of the input signal having a first frequency. The first differential circuit provides a first output signal that is twice the frequency and is in phase(0) based on the 0 the 180 phase components of the input signal. The apparatus also includes a second differential circuit that is capable of receiving a 90 phase component of the input signal and a 270 phase component of the input signal, and provide a first output signal that is twice the frequency and out of phase(180). The apparatus also includes a differential transformer that is configured to receive the first output signal and the second output signal. The differential transformer is configured to provide a differential output signal that has a second frequency that is twice the first frequency.