H03B19/00

Reference signal path for clock generation with an injection locked multiplier (ILM)

Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.

Variable frequency divider

A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

Frequency tripler and method thereof
10411680 · 2019-09-10 · ·

A circuit includes a first TSCP (tri-state charge pump) configured to receive a first phase and a third phase of a six-phase signal; a second TSCP configured to receive a second phase and a fourth phase of the six-phase signal; a third TSCP configured to receive a third phase and a fifth phase of the six-phase signal; a fourth TSCP configured to receive a fourth phase and a sixth phase, a fifth TSCP configured to receive the fifth phase and the first phase, and a sixth TSCP configured to receive the sixth phase and the second phase of the six-phase signal. The first, third, and fifth TSCPs output currents to a first output node and the second, fourth, and sixth TSCPs output currents to a second output node. A load is placed across the first output node and the second output node.

Integrated circuit comprising fractional clock multiplication circuitry

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Integrated circuit comprising fractional clock multiplication circuitry

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Predictive electronic thermometer circuit structure capable of temperature compensation
11976986 · 2024-05-07 ·

A predictive electronic thermometer circuit structure capable of temperature compensation is provided, including: a compensation module, a thermometer circuit, and a liquid crystal display (LCD) drive module. The thermometer circuit includes a temperature measurement oscillation circuit and a real measurement module. The compensation module and the real measurement module are connected in parallel between the temperature measurement oscillation circuit and the LCD drive module. The predictive electronic thermometer circuit structure controls the on and off of the compensation module and the real measurement module through a combination logic control switch respectively. When the compensation module is off and the real measurement module is on, an actual measured data is output. When the real measurement module is off and the compensation module is on, a temperature value is output after predictive compensation. The electronic thermometer has a temperature compensation function, and measures the temperature quickly and accurately.

Clock divide-by-three circuit
10379570 · 2019-08-13 · ·

A clock divider circuit receives an input clock signal having a first frequency (f) and generates an output signal having a frequency equal to f/N, where N is an odd integer. The clock divider circuit includes an edge counter to count a number of consecutive edges of the input clock signal having a first plurality, and to assert a control signal when a threshold number (N) of consecutive edges has been counted. The clock divider circuit also includes a frequency multiplier to generate an intermediate clock signal having a frequency equal to 2f/N by doubling the frequency of the control signal based at least in part on transitions of the input clock signal, and a frequency divider to generate an output clock signal having a frequency equal to f/N by halving the frequency of the intermediate clock signal.

Harmonic multiplier architecture

A method and system of providing harmonic frequency multiplication are provided. An input signal having a frequency f, is received by a programmable timing circuit. A signal that is in phase with the input signal, is provided at the first output of the programmable timing circuit. A time delayed version of the input signal, having the frequency f, is provided at the second output of the programmable timing circuit. A signal having the frequency f, is provided at the output of a first buffer. A duty cycled controlled signal having the frequency f, is provided at the output of the second buffer. A frequency nf, where n is a positive integer, is provided at the output of the multiplier. A higher-order frequency multiplied signal based on the frequencies f and nf, is provided at the output of a mixer.

Non-linear transmission line device
10263565 · 2019-04-16 · ·

A non-linear transmission line device includes a magnetic element having at least one end profiled to reduce demagnetization when the element is biased. The profile may be tapered, stepped, or smoothly curved. Also disclosed is a non-linear transmission device made up of a solid magnetic element, typically of flat rectangular form.

Non-linear transmission line device
10263565 · 2019-04-16 · ·

A non-linear transmission line device includes a magnetic element having at least one end profiled to reduce demagnetization when the element is biased. The profile may be tapered, stepped, or smoothly curved. Also disclosed is a non-linear transmission device made up of a solid magnetic element, typically of flat rectangular form.