Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal.

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Some demonstrative embodiments include devices, systems and/or methods of generating a frequency reference using a solid-state atomic resonator formed by a solid-state material including an optical cavity having color centers. A device may include a solid-state atomic clock to generate a clock frequency signal, the solid-state atomic clock including a solid state atomic resonator formed by a solid-state material including an optical cavity having color centers, which are capable of exhibiting hyperfine transition, wherein the solid-state atomic clock may generate the clock frequency signal based on a hyperfine resonance frequency of the color centers.

Some demonstrative embodiments include devices, systems and/or methods of generating a frequency reference using a solid-state atomic resonator formed by a solid-state material including an optical cavity having color centers. A device may include a solid-state atomic clock to generate a clock frequency signal, the solid-state atomic clock including a solid state atomic resonator formed by a solid-state material including an optical cavity having color centers, which are capable of exhibiting hyperfine transition, wherein the solid-state atomic clock may generate the clock frequency signal based on a hyperfine resonance frequency of the color centers.

A system and method for adjusting a clock signal of a seismic data acquisition system. The system includes a data acquisition device having an oscillator that generates a clock signal; a clock adjustment module that receives a time reference signal and the clock signal and outputs an adjusted clock signal; and an analog-to-digital convertor configured to transform analog data into digital data having a sampling rate (F.sub.DATA). A sampling frequency (f.sub.ADC) of the analog-to-digital convertor is selected to be at least twice the sampling rate (F.sub.DATA).

A frequency tripler includes a double-frequency in-phase signal generator, a double-frequency quadrature signal generator and a mixer. The double-frequency in-phase signal generator is arranged for receiving at least an in-phase signal and a quadrature signal to generate a double-frequency in-phase signal whose frequency is twice that of the in-phase signal or the quadrature signal; the double-frequency quadrature signal generator is arranged for receiving at least the in-phase signal and the quadrature signal to generate a double-frequency quadrature signal whose frequency is twice that of the in-phase signal or the quadrature signal; and the mixer is arranged for receiving the in-phase signal, the quadrature signal, the double-frequency in-phase signal and the double-frequency quadrature signal to generate an output signal whose frequency is triple that of the in-phase signal or the quadrature signal.

The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.

A clock signal generator responsive to synchronization pulses to perform actions has a phase locked loop (PLL) part including a digitally controlled oscillator (DCO) and an output driver coupled to the DCO, and a synthesizer part including a frequency synthesizer responsive to frequency and phase information from the DCO to generate a synthesized clock and programmable output dividers for generating output clocks from the synthesized clock. An interface establishes communication between the PLL part and the synthesizer part. The output driver is programmed to compute a phase offset required to align a selected output divider with the phase of the DCO and transmit the computed offset to the selected output divider over said interface for application to said selected output divider upon the occurrence of a synchronization pulse.