A charger including a class E power driver, a frequency-shift keying (“FSK”) module, and a processor. The processor can receive data relating to the operation of the class E power driver and can control the class E power driver based on the received data relating to the operation of the class E power driver. The processor can additionally control the FSK module to modulate the natural frequency of the class E power transformer to thereby allow the simultaneous recharging of an implantable device and the transmission of data to the implantable device. The processor can additionally compensate for propagation delays by adjusting switching times.

An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

A device includes a plurality of phase accumulators, a multiplexer, and an oscillator. The plurality of phase accumulators is configured to receive a plurality of frequencies and generate a plurality of ramp signals. The multiplexer is configured to receive the plurality of ramp signals from the plurality of phase accumulators and to select one ramp signal from the plurality of ramp signals. The oscillator is configured to receive the one selected ramp signal and to generate one amplitude signal associated therewith. The plurality of phase accumulators continues generating their respective ramp signal. The multiplexer subsequent to selecting the one ramp signal is configured to select another ramp signal associated with another one phase accumulator of the plurality of phase accumulators. The oscillator is further configured to receive the selected another ramp signal and to generate another amplitude signal associated therewith.

A device includes a plurality of phase accumulators, a multiplexer, and an oscillator. The plurality of phase accumulators is configured to receive a plurality of frequencies and generate a plurality of ramp signals. The multiplexer is configured to receive the plurality of ramp signals from the plurality of phase accumulators and to select one ramp signal from the plurality of ramp signals. The oscillator is configured to receive the one selected ramp signal and to generate one amplitude signal associated therewith. The plurality of phase accumulators continues generating their respective ramp signal. The multiplexer subsequent to selecting the one ramp signal is configured to select another ramp signal associated with another one phase accumulator of the plurality of phase accumulators. The oscillator is further configured to receive the selected another ramp signal and to generate another amplitude signal associated therewith.

The transmitter includes a digital modulator adapted to provide a digital modulated RF signal based on a multi-bit representation of data and a multi-bit representation of a carrier wave. A digital-to-analog converter (DAC) is adapted to generate an analog modulated RF signal based on the digital modulated RF signal. A resonant circuit coupled to an output of the DAC and adapted to filter undesired frequency components from the analog modulated RF signal.

An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

Techniques for mixing, or modulating, a high-frequency, digital communication signal with a low-frequency, analog current loop signal are provided. In certain examples, the techniques allow mixing the signals in a non-AC coupled manner. In certain examples, such mixing techniques can allow for simplified connections between a modem chip and an analog current loop interface chip of an analog I/O module.

A charger including a class E power driver, a frequency-shift keying (FSK) module, and a processor. The processor can receive data relating to the operation of the class E power driver and can control the class E power driver based on the received data relating to the operation of the class E power driver. The processor can additionally control the FSK module to modulate the natural frequency of the class E power transformer to thereby allow the simultaneous recharging of an implantable device and the transmission of data to the implantable device. The processor can additionally compensate for propagation delays by adjusting switching times.

A charger including a class E power driver, a frequency-shift keying (FSK) module, and a processor. The processor can receive data relating to the operation of the class E power driver and can control the class E power driver based on the received data relating to the operation of the class E power driver. The processor can additionally control the FSK module to modulate the natural frequency of the class E power transformer to thereby allow the simultaneous recharging of an implantable device and the transmission of data to the implantable device. The processor can additionally compensate for propagation delays by adjusting switching times.