Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

A method of determining a phase misalignment between a first signal generated from a first signal path and a second signal generated from a second signal path may include obtaining multiple samples of the first signal proximate to when the first signal crosses zero wherein the first signal can be approximated as linear; obtaining multiple samples of the second signal proximate to when the second signal crosses zero wherein the first signal can be approximated as linear; based on the multiple samples of the first signal, approximating a first time at which the first signal crosses zero; based on the multiple samples of the second signal, approximating a second time at which the second signal crosses zero; and determining the phase misalignment between the first signal and the second signal based on a difference between the first time and the second time.

A frequency detector is used for detecting a frequency difference of a signal to be tested from a first time point to a second time point. The frequency detector includes: an alternating current coupled capacitor configured to receive the signal to be tested; a rectifying circuit electrically connected to the alternating current coupled capacitor; an analog-to-digital converter electrically connected to the rectifying circuit; a control unit electrically connected to the analog-to-digital converter; and a counter electrically connected to the rectifying circuit and the control unit, wherein the control unit is configured to calculate the frequency difference of the signal to be tested from the first time point to the second time point according to outputs of the analog-to-digital converter and outputs of the counter.

A fast phase frequency includes two fast pulsed-latches, a NAND gate, and an adjustable delay circuit, where the fast pulsed-latches include a pulse generating circuit, a reset circuit, and an output latch circuit. The pulse generating circuit is configured to generate a power supply pulse signal when a rising edge of the clock signal arrives, the power supply pulse signal causing the input of the output latch circuit to be a low level. The output latch circuit is configured to maintain its current output state when the clock signal or the reset signal is invalid, and the reset circuit is configured to set the input of the output latch circuit to be a high level. By using fast pulsed-latches with clock and reset control, the fast phase frequency detector shortens the reset loop delay and increases the maximum operating frequency of the phase frequency detector.

A fast phase frequency includes two fast pulsed-latches, a NAND gate, and an adjustable delay circuit, where the fast pulsed-latches include a pulse generating circuit, a reset circuit, and an output latch circuit. The pulse generating circuit is configured to generate a power supply pulse signal when a rising edge of the clock signal arrives, the power supply pulse signal causing the input of the output latch circuit to be a low level. The output latch circuit is configured to maintain its current output state when the clock signal or the reset signal is invalid, and the reset circuit is configured to set the input of the output latch circuit to be a high level. By using fast pulsed-latches with clock and reset control, the fast phase frequency detector shortens the reset loop delay and increases the maximum operating frequency of the phase frequency detector.

A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.

A time detection circuit and a time detection method are provided. The time detection circuit includes an input signal processor and a time signal amplifier. The input signal processor receives a first input signal and a second input signal, calculates a time difference value between the first input signal and the second input signal, adjusts the time difference value by comparing the time difference value with a set reference value, and provides the adjusted time difference value. The time signal amplifier receives the adjusted time difference value, and amplifies the adjusted time difference value to generate an amplified time signal. The time signal amplifier operates in a linear operation region between a first time value and a second time value, and the set reference value is set according to the first time value and the second time value.

Disclosed a fast phase frequency detector, comprising: two fast pulsed-latches, a NAND gate and an adjustable delay circuit. The fast pulsed-latches comprises: a pulse generating circuit, a reset circuit, and an output latch circuit; the pulse generating circuit is configured to generate a power supply pulse signal when a rising edge of the clock signal arrives, the power supply pulse signal causing the input of the output latch circuit to be a low level; the output latch circuit is configured to maintain its current output state when the clock signal or the reset signal is invalid; the reset circuit is configured to set the input of the output latch circuit to be a high level. By using fast pulsed-latches with clock and reset control, the fast phase frequency detector of the present application shortens the reset loop delay and increases the maximum operating frequency of the phase frequency detector.