Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.

A frequency detector is used for detecting a frequency difference of a signal to be tested from a first time point to a second time point. The frequency detector includes: an alternating current coupled capacitor configured to receive the signal to be tested; a rectifying circuit electrically connected to the alternating current coupled capacitor; an analog-to-digital converter electrically connected to the rectifying circuit; a control unit electrically connected to the analog-to-digital converter; and a counter electrically connected to the rectifying circuit and the control unit, wherein the control unit is configured to calculate the frequency difference of the signal to be tested from the first time point to the second time point according to outputs of the analog-to-digital converter and outputs of the counter.

Described herein is an apparatus for the recovery of asynchronous data into a fixed clock domain. A phase-locked loop (PLL) of the known art is replaced by a modified quadrature resolver, and the output from the resolver re-creates the selected frequency component of the input asynchronous data. The zero-crossings of this re-created data clock are used to sample the input data stream. One advantage of this technique is that it operates as a state machine on a single clock, and no analog components such as phase detectors or VCOs are needed. In another embodiment, the samples from the input data stream are changed from pulses to Gaussians, allowing for conversion of the sample rate from one clock domain to another.

A count processor counts a zero crossing detection count C. A fraction processor for calculating a fraction F.sub.j (j=1 to L) of the zero crossing detection count on the basis of the digital signal at sampling timings immediately before a zero crossing specifying and when the zero crossing specifying, and computing a fraction processing parameter G.sub.j=N.sub.jF.sub.j using a zero crossing detection number N.sub.j(0N.sub.jN1) in a period corresponding to a sampling count N necessary for averaging determined in advance. The averaging is performed according to the following formula, where C is the output of the count processor at the end of an averaging period and G.sub.j (j=1 to L) is L fraction processing parameters (L indicates the number of G.sub.j included between the averaging counts N) computed by the fraction processor, and the phase of the digital signal is computed, whereby the phase is calculated on the basis of an input signal digital value obtained by an AD converter. $\begin{array}{cc}U=C-\frac{1}{N}\underset{j=1}{\overset{L}{.Math.}}{G}_j& \left(\mathrm{Formula}1\right)\end{array}$

A count processor counts a zero crossing detection count C. A fraction processor for calculating a fraction F.sub.j (j=1 to L) of the zero crossing detection count on the basis of the digital signal at sampling timings immediately before a zero crossing specifying and when the zero crossing specifying, and computing a fraction processing parameter G.sub.j=N.sub.jF.sub.j using a zero crossing detection number N.sub.j(0N.sub.jN1) in a period corresponding to a sampling count N necessary for averaging determined in advance. The averaging is performed according to the following formula, where C is the output of the count processor at the end of an averaging period and G.sub.j (j=1 to L) is L fraction processing parameters (L indicates the number of G.sub.j included between the averaging counts N) computed by the fraction processor, and the phase of the digital signal is computed, whereby the phase is calculated on the basis of an input signal digital value obtained by an AD converter. $\begin{array}{cc}U=C-\frac{1}{N}\underset{j=1}{\overset{L}{.Math.}}{G}_j& \left(\mathrm{Formula}1\right)\end{array}$

An apparatus for phase and frequency detection (PFD) includes a first circuit to receive a first input pulse and to generate a first output pulse, the rising edge of which is triggered by a first rising edge of the first input pulse, and a second circuit coupled to the first circuit and configured to receive a second input pulse and to generate a second output pulse, the rising edge of which is triggered by a second rising edge of the second input pulse. The second output pulse has a falling edge carrying first information related to a first rising edge of the first input pulse. The first output pulse has a falling edge carrying second information related to a second rising edge of the second input pulse.

An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring.

An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring.

Described herein is an apparatus for the recovery of asynchronous data into a fixed clock domain. A phase-locked loop (PLL) of the known art is replaced by a modified quadrature resolver, and the output from the resolver re-creates the selected frequency component of the input asynchronous data. The zero-crossings of this re-created data clock are used to sample the input data stream. One advantage of this technique is that it operates as a state machine on a single clock, and no analog components such as phase detectors or VCOs are needed. In another embodiment, the samples from the input data stream are changed from pulses to Gaussians, allowing for conversion of the sample rate from one clock domain to another.

Embodiments of a phase difference estimator and method are generally described herein. The phase difference estimator includes a delay element to delay a reference clock signal that includes an alternating symbol waveform by one of a plurality of delay values. The phase difference estimator further includes a sampler to sample a monitored clock signal provided by a second device responsive to edges of the delayed reference clock signal to generate a sampled signal output. The phase difference estimator further includes a correlation element to correlate the sampled signal output of the sampler with a step function to generate a correlation value for each delay value, and a controller to instruct the delay element to delay the reference clock signal by one of the delay values and provide a phase difference estimate output indicative of a phase difference between the reference and monitored clock signals based on the correlation value.