Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

Embodiments of the present disclosure disclose a clock frequency detection method and apparatus. The method includes: dividing a known internal clock frequency range of the system into n frequency intervals, where each frequency interval is corresponding to a frequency detection module, and n is an integer greater than or equal to 2; obtaining a current internal clock frequency of the system, and using the current internal clock frequency as a reference clock frequency; selecting a frequency detection module corresponding to a frequency interval according to the reference clock frequency; and detecting, by the selected frequency detection module, a to-be-detected clock according to a frequency offset range of the reference clock frequency. By using the present disclosure, a risk that an internal clock of the system is attacked may be reduced, and system security may be improved.

A temperature-compensated resonant MEMS device comprises a first and second oscillator circuits comprising a first and second resonant MEMS devices and providing a first and second oscillator outputs. One of the resonant MEMS devices is a temperature reference for the other. A level-sensitive mixer circuit has first and second inputs coupled to the first and second oscillator outputs and has a mixer output to provide a signal responsive to a level of the first and second oscillator outputs. The mixer output comprises sum and difference frequency components of the first and second oscillator outputs. A low-pass filter is coupled to the mixer output to attenuate the sum frequency component of the mixer output. An output coupled to an output of said low-pass filter provides a signal responsive to the difference frequency component.

A method and device for sorting grounded electrical conductors according to phase. Different high-current pulsed sequences are applied to each of the electrical conductors of a first three-phase conductor in an electrical power network. Pulsed current sequences applied to the three electrical conductors of the first conductor, seeking an electrical ground, will be detectable on the electrical conductors of each of the conductors in parallel with the electrical conductors of the first conductor. A detector detects a magnetic-pulsed sequence associated with the current-pulsed sequences on the electrical conductors and matches it to one of the corresponding current-pulsed sequences on the electrical conductors of the first three-phase conductor, thereby decoding the sequence to identify the phases of each of the conductors. Each electrical conductor is then tagged with its phase before the conductor network is ungrounded and energized.

Given a node of a utility service distribution network, a topology of a subset of the distribution network having the given node as a root node and one or more child nodes branching from the given node is determined. The topology may be determined based on relationships or correlations of utility usage information between the given node and a plurality of potential nodes that are considered in the topology determination. Upon determining the topology associated with the given node, the determined topology may be used to detect fraud and leakage that may occur in the distribution network on a regular basis or upon request. If fraud or leakage is detected in the distribution network, the system may schedule a follow-up and/or field investigation to investigate and fix the fraud or the leakage in the distribution network.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

The method determines an input phase differential () between two input signals. A phase detector is provided that has pairs of transistors and a first impedance (R1) connected to a first branch carrying a first signal (Iout_left) and a second impedance (R2) connected to a second branch carrying a second signal (Iout_right). The first signal (Iout_left) in the first branch is set as a first sum of a common mode output signal (Icm) and a differential mode output signal (Idm). The second signal (Iout_right) in the second branch is set as a second sum of the common mode output signal (Icm) minus the differential mode output signal (Idm). A relationship between the first impedance (R1) and the second impedance (R2) is adjusted until a differential mode output voltage (Vdm) of the phase detector is zero. The input phase differential () is determined when the differential mode output voltage (Vdm) is zero.

In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.