The method determines an input phase differential () between two input signals. A phase detector is provided that has pairs of transistors and a first impedance (R1) connected to a first branch carrying a first signal (Iout_left) and a second impedance (R2) connected to a second branch carrying a second signal (Iout_right). The first signal (Iout_left) in the first branch is set as a first sum of a common mode output signal (Icm) and a differential mode output signal (Idm). The second signal (Iout_right) in the second branch is set as a second sum of the common mode output signal (Icm) minus the differential mode output signal (Idm). A relationship between the first impedance (R1) and the second impedance (R2) is adjusted until a differential mode output voltage (Vdm) of the phase detector is zero. The input phase differential () is determined when the differential mode output voltage (Vdm) is zero.

A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.

An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.

Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.