A phase compensation circuit, being for compensating phase of a first voltage inputted to a PWM comparator of a DC/DC converter having a sleep mode, includes: a phase compensation resistor part including a resistor; a phase compensation capacitor part including a plurality of capacitors; and a switch group arranged to change over the capacitors, in the sleep mode, to a first connection state in which at least one of the capacitors is charged with a first bias voltage and to change over the capacitors, at cancellation of the sleep mode, to a second connection state in which the first voltage is set to a desired initial value.

Circuits and methods for biasing power amplifiers. In some embodiments, a power amplifier circuit can include a transistor having and input and an output, and configured to amplify a signal. The power amplifier circuit can further include a bias circuit configured to provide a bias signal to the input of the transistor. The power amplifier circuit can further include a switchable feed circuit implemented between the bias circuit and the input of the transistor, and configured to provide a plurality of different resistance values for the bias signal between the bias circuit and the input of the transistor.

An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

An apparatus for controlling the gain and phase of an input signal input to a power amplifier comprises a gain control loop configured to control the gain of the input signal based on power levels of the input signal and an amplified signal output by the power amplifier, to obtain a predetermined gain of the amplified signal, and a phase control loop configured to obtain an error signal related to a phase difference between a first signal derived from the input and a second signal derived from the amplified signal, and control the phase based on the error signal, to obtain a predetermined phase of the amplified signal. The phase control loop delays the first signal such that the delayed first signal and the second signal used to obtain the error signal correspond to the same part of the input signal. The apparatus may be included in a satellite.

A programmable gain amplifier includes an active load module, a first differential pair, a second differential pair and a power source module. The first and second differential pairs are electrically connected to the active load module. The power source module is electrically connected to the first current source end of the first differential pair and the second current source end of the second differential pair. The power source module supplies a first current to the first differential pair through the first current source end. The power source module supplies a second current to the second differential pair through the second current source end. The power source module adjusts the potential of the first current, the potential of the second current, or both.

A headphone driver, a sound processor that incorporates the headphone driver and a computing system that incorporates the headphone driver, wherein the headphone driver includes an amplifier having an input terminal and an output terminal, an R-2R ladder network provided with an input signal and connected to the input terminal of the amplifier, and a feedback resistor group connected to the input terminal and to the output terminal of the amplifier. The R-2R ladder network includes a plurality of resistor branches and a first attenuator that is connected between the plurality of resistor branches.

A switch-mode RFPA driver includes first and second field-effect transistors (FETs) arranged in a totem-pole-like configuration. The switch-mode RFPA driver operates to generate a switch-mode RFPA drive signal having a generally square-wave-like waveform from an input RF signal having a generally sinusoidal-like waveform. According to one embodiment of the invention, to maximize high-frequency operation and avoid distorting the switch-mode RFPA drive signal, the switch-mode RFPA driver is designed so that its output can be connected directly to the input of the switch-mode RFPA to be driven, i.e., without using or requiring the use of an AC coupling capacitor. The first and second FETs of the switch-mode RFPA driver are designed and configured to limit and control the upper and lower magnitude levels of the switch-mode RFPA drive signal to levels suitable for switching the switch-mode RFPA directly, obviating any need for DC biasing at the input of the switch-mode RFPA.

In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain.

A power amplifier gain attenuation circuit includes: a gain attenuation (reduction) circuit configured to receive an input signal, an external drive signal and a bias voltage, and output a secondary input signal after attenuating the input signal depending on the drive signal and bias voltage; an amplifier including: a bias input terminal configured to receive a bias voltage; a signal input terminal configured to receive a secondary input signal, and an output terminal configured to output a gained output signal. The power amplifier gain attenuation circuit can reduce a gain effectively, and the amount of phase jump caused by the attenuation is quite small.