Patent classifications
H03H1/00
RF REFERENCE MEASURING CIRCUIT FOR A DIRECT DRIVE SYSTEM SUPPLYING POWER TO GENERATE PLASMA IN A SUBSTRATE PROCESSING SYSTEM
A substrate processing system includes a drive circuit, an RF reference measuring circuit, and a make-break connector. The drive circuit generates an RF drive signal at a first RF frequency. The RF reference measuring circuit includes an LC circuit having an input impedance and an output impedance. An output of the LC circuit connects to an RF power meter and a dummy load. The make-break connector connects the drive circuit to one of the RF reference measuring circuit and a processing chamber load including a component of the substrate processing system. An output impedance of the drive circuit matches an impedance of an input impedance of the LC circuit. The output impedance of the drive circuit does not match impedances of the RF power meter and the dummy load. The LC circuit matches the impedance of the drive circuit to the RF power meter and the dummy load.
Communication on two power supply channels
A Communication System includes a first power supply channel including a first impedance and a second impedance, and configured to transfer electrical power from a first power source to a first load. The first power supply channel is configured to electrically couple to the first power source via a first common mode choke. The communication system also includes a second power supply channel comprising a third impedance and a fourth impedance, and configured to transfer electrical power from a second power source to a second load. The second power supply channel is configured to electrically couple to the second power source via a second common mode choke. The communication system further includes a first transceiver comprising a first output pin electrically coupled to the first power supply channel and a second output pin electrically coupled to the second power supply channel at a first end of the communication system.
FILTERED FEEDTHROUGH ASSEMBLY FOR USE IN IMPLANTABLE MEDICAL DEVICE
An implantable pulse generator including a header, a can, and a filtered feedthrough assembly. The header including lead connector blocks. The can coupled to the header and including a wall and an electronic substrate housed within the wall. The filtered feedthrough assembly including a flange mounted to the can and having a feedthrough port, a plurality of feedthrough wires extending through the feedthrough port, and an insulator brazed to the feedthrough port of the flange. The filtered feedthrough assembly further including a capacitor having the plurality of feedthrough wires extending there through, an insulating washer positioned between and abutting the insulator and the capacitor at least in the area of the braze joint such that the capacitor and the braze joint are non-conductive, and an electrically conductive material adhered to the capacitor and the flange for grounding of the capacitor.
FILTERED FEEDTHROUGH ASSEMBLY FOR USE IN IMPLANTABLE MEDICAL DEVICE
An implantable pulse generator including a header, a can, and a filtered feedthrough assembly. The header including lead connector blocks. The can coupled to the header and including a wall and an electronic substrate housed within the wall. The filtered feedthrough assembly including a flange mounted to the can and having a feedthrough port, a plurality of feedthrough wires extending through the feedthrough port, and an insulator brazed to the feedthrough port of the flange. The filtered feedthrough assembly further including a capacitor having the plurality of feedthrough wires extending there through, an insulating washer positioned between and abutting the insulator and the capacitor at least in the area of the braze joint such that the capacitor and the braze joint are non-conductive, and an electrically conductive material adhered to the capacitor and the flange for grounding of the capacitor.
RECONFIGURABLE INTELLIGENT SURFACE REALIZED WITH INTEGRATED CHIP TILING
Disclosed is an electromagnetic-circuit co-design approach for massively reconfigurable, multifunctional, and high-speed programmable metasurfaces with integrated chip tiling. The ability to manipulate the incident electromagnetic fields in a dynamically programmable manner and at high speeds using integrated chip tiling approach is also disclosed. The scalable architecture uses electromagnetic-circuit co-design of metasurfaces where each individual subwavelength meta-element is uniquely addressable and programmable. The disclosed device comprises a large array of such meta-elements. The design relies on integrated high frequency switches designed in conjugation with meta-element for massive reconfigurability of incident amplitude and phase. The disclosed chip is multi-functional and can perform beamforming, high speed spatial light modulation, dynamic holographic projections, and wavefront manipulation.
Ground electrical path from an MLCC filter capacitor on an AIMD circuit board to the ferrule of a hermetic feedthrough
An EMI/energy dissipating filter for an active implantable medical device (AIMD) comprises a first gold braze sealing an insulator to the ferrule of a glass-to-metal seal (GTMS) and a lead wire that is sealed in a passageway through the insulator by a second gold braze. A circuit board is disposed adjacent to the insulator. A two-terminal chip capacitor disposed adjacent to the circuit board has an active end metallization connected to its active electrode plates and a ground end metallization connected to its ground electrode plates. A ground electrical path extends from the ground end metallization of the chip capacitor, through a circuit board ground plate disposed on or within the circuit board, and to the ferrule. An active electrical path extends from the active end metallization of the chip capacitor to the lead wire of the GTMS.
Ground electrical path from an MLCC filter capacitor on an AIMD circuit board to the ferrule of a hermetic feedthrough
An EMI/energy dissipating filter for an active implantable medical device (AIMD) comprises a first gold braze sealing an insulator to the ferrule of a glass-to-metal seal (GTMS) and a lead wire that is sealed in a passageway through the insulator by a second gold braze. A circuit board is disposed adjacent to the insulator. A two-terminal chip capacitor disposed adjacent to the circuit board has an active end metallization connected to its active electrode plates and a ground end metallization connected to its ground electrode plates. A ground electrical path extends from the ground end metallization of the chip capacitor, through a circuit board ground plate disposed on or within the circuit board, and to the ferrule. An active electrical path extends from the active end metallization of the chip capacitor to the lead wire of the GTMS.
Systems and methods for an inductor structure having an unconventional turn-ratio in integrated circuits
Embodiments described herein provide circuitry employing one or more inductors having an unconventional turn-ratio. The circuitry includes a primary inductor having a first length located on a first layer of an integrated circuit (IC). The circuitry further includes a secondary inductor having a second length located on a second layer of the IC different from the first layer, whereby the second length is greater than the first length, with a ratio between the first and the second lengths corresponding to a non-integer turn-ratio.
Systems and methods for an inductor structure having an unconventional turn-ratio in integrated circuits
Embodiments described herein provide circuitry employing one or more inductors having an unconventional turn-ratio. The circuitry includes a primary inductor having a first length located on a first layer of an integrated circuit (IC). The circuitry further includes a secondary inductor having a second length located on a second layer of the IC different from the first layer, whereby the second length is greater than the first length, with a ratio between the first and the second lengths corresponding to a non-integer turn-ratio.
High performance tunable filter
Disclosed is a gallium arsenide (GaAs) enabled tunable filter for, e.g., 6 GHz Wi-Fi RF Frontend, with integrated high-performance varactors, metal-insulator-metal (MIM) capacitors, and 3D solenoid inductors. The tunable filter comprises a hyper-abrupt variable capacitor (varactor) high capacitance tuning ratio. The tunable filter also comprises a GaAs substrate in which through-GaAs-vias (TGV) are formed. The varactor along with the MIM capacitors and the 3D inductors is formed in an upper conductive structure on upper surface of the GaAs substrate. Lower conductive structure comprising lower conductors is formed on lower surface of the GaAs substrate. Electrical coupling between the lower and upper conductive structures is provided by the TGVs. The tunable filter can be integrated with radio frequency front end (RFFE) devices.