Embodiments of the present disclosure provide apparatuses and methods for balancing parasitic capacitances between metal tracks in an integrated circuit chip. Specifically, additional capacitances in the form of, for example, tab capacitors, are attached to the metal tracks with the intention of detaching a select number of the attached capacitances for the purpose of balancing the parasitic capacitances between the metal tracks. The attached capacitances may be structural metal elements. Further, the attached structural metal elements may be detachable at thin-film resistive material associated with each of the attached structural metal elements.

Embodiments of the present disclosure provide apparatuses and methods for balancing parasitic capacitances between metal tracks in an integrated circuit chip. Specifically, additional capacitances in the form of, for example, tab capacitors, are attached to the metal tracks with the intention of detaching a select number of the attached capacitances for the purpose of balancing the parasitic capacitances between the metal tracks. The attached capacitances may be structural metal elements. Further, the attached structural metal elements may be detachable at thin-film resistive material associated with each of the attached structural metal elements.

The present invention includes a method for creating a system-in-package in or on photodefinable glass including: providing a photodefinable glass substrate; masking a design layout comprising one or more structures to form one or more integrated lumped element devices as the system-in-package on or in a photodefinable glass substrate; transforming at least a portion of the photodefinable glass substrate to form a glass-crystalline substrate; etching the glass-crystalline substrate to form one or more channels in the glass-crystalline substrate; depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate to enable electroplating of copper; and electroplating the copper to fill the one or more channels and to deposit copper on the surface of the photodefinable glass to form the one or more integrated lumped element devices.

The present invention includes a method for creating a system-in-package in or on photodefinable glass including: providing a photodefinable glass substrate; masking a design layout comprising one or more structures to form one or more integrated lumped element devices as the system-in-package on or in a photodefinable glass substrate; transforming at least a portion of the photodefinable glass substrate to form a glass-crystalline substrate; etching the glass-crystalline substrate to form one or more channels in the glass-crystalline substrate; depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate to enable electroplating of copper; and electroplating the copper to fill the one or more channels and to deposit copper on the surface of the photodefinable glass to form the one or more integrated lumped element devices.

A high frequency multilayer filter may include a plurality of dielectric layers and a signal path having an input and an output. The multilayer filter may include an inductor including a conductive layer formed over a first dielectric layer. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The multilayer filter may include a capacitor including a first electrode and a second electrode that is separated from the first electrode by a second dielectric layer. The multilayer filter has a characteristic frequency that is greater than about 6 GHz

A high frequency multilayer filter may include a plurality of dielectric layers and a signal path having an input and an output. The multilayer filter may include an inductor including a conductive layer formed over a first dielectric layer. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The multilayer filter may include a capacitor including a first electrode and a second electrode that is separated from the first electrode by a second dielectric layer. The multilayer filter has a characteristic frequency that is greater than about 6 GHz

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.

Provided is a laminated electronic component in which defective formation is unlikely to cause in a shield conductor layer on a side surface of a laminate. The laminated electronic component includes a laminate 1, in which substrate layers 1a to 1i are laminated, having an outer surface including a first main surface 1B, a second main surface 1T, and a side surface 1S, internal electrodes (a ground electrode 2, coil electrodes 3, capacitor electrodes 4, and wiring electrodes 5), an external electrode 7, and a first plating layer 9 formed on a surface of the external electrode 7.

Provided is a laminated electronic component in which defective formation is unlikely to cause in a shield conductor layer on a side surface of a laminate. The laminated electronic component includes a laminate 1, in which substrate layers 1a to 1i are laminated, having an outer surface including a first main surface 1B, a second main surface 1T, and a side surface 1S, internal electrodes (a ground electrode 2, coil electrodes 3, capacitor electrodes 4, and wiring electrodes 5), an external electrode 7, and a first plating layer 9 formed on a surface of the external electrode 7.