A radiofrequency filter utilizing a common mode choke both as a traditional common mode choke as well as the inductance in a low pass filter. Filter topology as well as component selection is optimized for wide band operation. Common mode chokes allow differential currents to pass with little attenuation while common mode currents are effectively presented with an inductance in the common current path. This inductance is used in a low pass filter configuration to present an even higher attenuation to common mode currents. The use of multiple chokes and/or differing core materials contributes to wider band operation without pronounced resonances. The capacitance used in the low pass filter is connected in a way as to reduce its effect on the data signals while still being effective in filtering.

A radiofrequency filter utilizing a common mode choke both as a traditional common mode choke as well as the inductance in a low pass filter. Filter topology as well as component selection is optimized for wide band operation. Common mode chokes allow differential currents to pass with little attenuation while common mode currents are effectively presented with an inductance in the common current path. This inductance is used in a low pass filter configuration to present an even higher attenuation to common mode currents. The use of multiple chokes and/or differing core materials contributes to wider band operation without pronounced resonances. The capacitance used in the low pass filter is connected in a way as to reduce its effect on the data signals while still being effective in filtering.

An equipment box assembly includes a housing including a back wall, a bottom wall, a top wall, and first and second sidewalls defining a cavity. At least one mounting feature is on each of the first and second sidewalls. The housing is sized to fit between first and second adjacent studs with the first sidewall mounted to the first stud using the at least one mounting feature on the first sidewall and with the second sidewall mounted to the second stud using the at least one mounting feature on the second sidewall.

An equipment box assembly includes a housing including a back wall, a bottom wall, a top wall, and first and second sidewalls defining a cavity. At least one mounting feature is on each of the first and second sidewalls. The housing is sized to fit between first and second adjacent studs with the first sidewall mounted to the first stud using the at least one mounting feature on the first sidewall and with the second sidewall mounted to the second stud using the at least one mounting feature on the second sidewall.

An integrated circuit device includes a first temperature sensor, a second temperature sensor, an A/D conversion circuit that performs A/D conversion on first and second temperature detection voltages from the first and second temperature sensors and outputs first and second temperature detection data, a digital signal processing circuit that generates frequency control data by performing a temperature compensation process by a neural network calculation process based on the first and second temperature detection data, and an oscillation signal generation circuit that generates an oscillation signal of a frequency set by the frequency control data using a resonator.

An integrated circuit device includes a digital signal processing circuit that generates frequency control data by performing a temperature compensation process by a neural network calculation process based on temperature detection data and an amount of change in time of the temperature detection data, and an oscillation signal generation circuit that generates an oscillation signal of a frequency set by the frequency control data using a resonator.

An integrated circuit device includes first and second temperature sensors, an A/D conversion circuit that performs A/D conversion on first and second temperature detection voltages from the first and second temperature sensors and outputs first and second temperature detection data, a connection terminal that is electrically connected to a temperature detection target device of the first and second temperature sensors, and a digital signal processing circuit that performs digital calculation based on the first and second temperature detection data and performs a temperature compensation process of correcting temperature characteristics of the temperature detection target device.

A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elements in the DIP is insignificant, removing the one insignificant circuit element from the DIP, deriving a final filter circuit design from the DIP, and manufacturing the microwave filter based on the final filter circuit design.

A splitter includes a common transmission line, a first transmission line, a second transmission line, a third transmission line, a fourth transmission line, a resistor, and a first reactance circuit. The common transmission line is coupled between a common port and a common node. The first transmission line is coupled between a first port and a first node. The second transmission line is coupled between a second port and a second node. The third transmission line is coupled between the common node and the first node. The fourth transmission line is coupled between the common node and the second node. The resistor is coupled between the first node and the second node. The first reactance circuit is coupled between the first node and the second node. The first reactance circuit includes a first inductor and a first capacitor coupled in parallel, but it does not include any resistor.

A splitter includes a common transmission line, a first transmission line, a second transmission line, a third transmission line, a fourth transmission line, a resistor, and a first reactance circuit. The common transmission line is coupled between a common port and a common node. The first transmission line is coupled between a first port and a first node. The second transmission line is coupled between a second port and a second node. The third transmission line is coupled between the common node and the first node. The fourth transmission line is coupled between the common node and the second node. The resistor is coupled between the first node and the second node. The first reactance circuit is coupled between the first node and the second node. The first reactance circuit includes a first inductor and a first capacitor coupled in parallel, but it does not include any resistor.