An equalizer circuit includes an phase-to-phase connectors including an phase-to-phase capacitor and four phase-to-phase switches, four output buffers, and control signal generation circuitry. One terminal of each phase-to-phase switches is connected to one of four connection paths on which four conversion signals being different in phase by 90 are input. The other one terminal of each phase-to-phase switches is connected to the phase-to-phase capacitor. Each output buffer is connected to one of the four connection paths and outputs an output signal. The control signal generation circuitry outputs control signals to control turning-on/off of the respective four phase-to-phase switches. A closing of the first, second, third, and fourth phase-to-phase switches are started from any one of phase-to-phase switches in one of a first ascending circulation and a first descending circulation based on the 4-phase control signals.

A charge sharing filter includes a rotating capacitor, and a plurality of elementary filters, each elementary filter comprising: an elementary switch coupled between a first node of the respective elementary filter and a second node of the respective elementary filter; and a history capacitor coupled to the first node of the respective elementary filter, wherein the second nodes of the plurality of elementary filters are interconnected with the rotating capacitor in one interconnecting node.

A digital/analog conversion apparatus to convert a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter to reduce the number of bits of an input signal, a second data converter to convert the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.

A digital/analog conversion apparatus to convert a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter to reduce the number of bits of an input signal, a second data converter to convert the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.

The present disclosure includes systems and techniques relating to time-varying notch filter. In one implementation, an apparatus includes a time-variant notch filter and a controller. The time-variant notch filter includes a notch depth and a notch bandwidth centered on a notch frequency. At least one of the notch depth or the notch bandwidth is based on a coefficient of the notch filter. The controller is configured to estimate a power of a packet being received and compare the estimated power of the packet to a predetermined threshold. The controller is also configured to set, conditioned on determining that the estimated power of the packet is greater than the predetermined threshold, a value of the coefficient to a first value such that the packet bypasses the time-variant notch filter.

There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.

There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.

There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.

Various signal processing techniques may benefit from appropriate handling. For example, certain signal processors may benefit from quarter wavelength unit delay and complex weight coefficient continuous-time filters. A method can include splitting an input signal into a plurality of signal paths. The method can also include complex weighting, for each signal path, a respective signal. The method can further include summing outputs of the signal paths. The method can additionally include providing an output comprising the sum of the signal paths. The complex weighting can be configured to independently control gain, phase and delay of the output signal over broadband.

A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal.